PD Basics 1

ASIC DESIGN TYPES

ASIC is mainly Divided into two Divisions
1)Logical Design(LD)
2)Physical Design(PD)

Physical Design  is Physical implementation of Design

• In Physical Design mainly Six inputs are present

1. Logical libraries      --> format is .lib    --->given by Vendors
2. physical libraries    -->format is .lef     --->given by vendors
3. Technology file       -->format is .tf       --->given by fabrication peoples
4. TLU+ file                   -->format is .TLUP-->given by fabrication people
5. Netlist                      --->format is .v       -->given by Synthesis People
6. Synthesis Design Constraints  -->format is .SDC   -->given by Synthesis People

    PHYSICAL DESIGN PROCESS.

1. DATA PREPARATION.
2. FLOOR PLAN.
3. POWER PLAN-->POWER ROUTING [PRE ROUTE]
4. PLACEMENT.-->[PRE CTS]
5. CLOCK TREE SYNTHESIS.-->CLOCK ROUTING.
6. ROUTING.-->DATA ROUTING.-->[POST ROUTE]
7. CHIP FINISHING.
8. VERIFICATION.
9. GDSII FILE.

LOGIC LIBRARIES

Logical libraries :format is .lib

1. Timing information of Standard cells,Soft macros,Hard macros.
2. functionality  information of Standard cells,Soft macros.
3. And design rules like max transition ,max capacitance, max fanout.
4. In timing information Cell delays ,Setup,Hold time are present.
5. Cell delay is Function of input transition and output load.
6. Cell delay is calculated based on lookup tables.
7. Cell delays are calculated by using linear delay models,Non linear delay models,CCS models.
8. functionality  is used for Optimization Purpose.
9. And also Contain Power information.
10. And contains Leakage power for Default cell,Leakage Power Density for cell,Default Input voltage , Out put voltage.

And PVT contains ------->Cell leakage Power
                                   -------->Internal Power
                                   --------->Rise Transition
                                  ----------->fall transition
                                   ---------->>Setup rise
                                  ----------->setup fall
                                  -------------->Hold rise
                                 ------------->Hold fall
                              ----------------->cell rise
                                ---------------->cell fal
                                -------------------->Pin Capacitance

And it contains A view(sub directory) i.e. LM(Logical Model view)view.
It contains logical libraries.

PHYSICAL LIBRARIES

Physical libraries: format is .lef:

1. physical information of std cells,macros,pads.
2. Pin information.
3. Define unit tile placement.
4. Minimum Width of Resolution.
5. Hight of the placement Rows .
6. Preferred routing Directions.
7. Pitch of the routing tracks.
8. Antena Rules.
9. Routing Blockages

In physical info height,area,width are present.
and also it contains two views
1)Cell View:
In this all layout information is present,it is used at the time of tapeout
2)FRAM view:
Fram view is abstract view, it is used at the Place & Route

TECHNOLOGY FILE

Technology file: format is .tf:

1. It contains Name,Number conventions of layer and via
2. It contains Physical,electrical characteristics of  layer and via
3. In Physical characteristics Min width,area,height are present.
4. In Electrical characteristics Current Density is present.
5. Units and Precisions of layer and via .
6. Colors and pattern of layer and via .
7. Physical Design rules of layer and via
8. In Physical Design rules Wire to Wire Spacing,Min Width between Layer and via are present.

TLU+

TLU+ files: format is .TLUP:

1. R,C parasitics of metal per unit length.
2. These(R,C parasitics) are used for calculating Net Delays.
3. If TLU+ files are not given then these are getting from .ITF file.
4. For Loading TLU+ files we have load three files .
5. Those are Max Tlu+,Min TLU+,MAP file.
6. MAP file maps the .ITF file and .tf file of the layer and via names.

NETLIST

Netlist: Format is .V

It contains Logical connectivity Of all Cell(Std cells,Macros).
It contain List of nets.
In the design for Knowing connectivity by using Fly lines.

SDC

SDC(Synopsys design Constraints) :Format is .SDC :

These Constraints are timing Constraints .
These Constraints used for to meet timing requirements.
Constraints are

1. CLOCK DEFINITIONS:Create Clock Period.
2. Generated Clock Definitions
3. Input Delay
4. Output Delay
5. I/O delay
6. Max delay
7. Min Delay
8. --------------->Exceptions<-------------------------
9. Multi cycle path
10. False path
11. Half cycle path
12. Disable timing arcs
13. Case Analysis

Multi cycle path, False path are Exceptions.

OPTIMIZATION CONTROLS

Design Optimization Controls :

1. Enable multiple clocks per register
2. Enable constant propagation
3. Enable multiple port net buffering
4. Enable Constant net buffering
5. Apply timing derating for On-Chip variations
6. Define Don't use or preferred cells
7. Keep Spare cells and unloaded cells
8. Apply area constraints and area recovery
9. Apply area and power cricalranges.
10. Organize paths into groups
11. Prevent clock as data networks
12. modify optimization priorities if needed
13. Enable recovery and removal check.