The motive of this group is to create awareness with in the student for VLSI/Semiconductor industry. If possible, I would like to create a link between experts and the students
If every employee in Semiconductor Industry take the responsibility of 1 candidate (fresher or just entered into the industry) and spend couple of Hrs. in a week, then we can change the whole world with in few months. -Fresher
Pages
▼
Friday, 27 February 2015
Difference between DIBL AND GIDL.
GIDL: Gate induced drain leakage is a leakage mechanism from the gate-drain overlap region caused when the Drain voltage is very high and Gate voltage is very low.The reverse biased pn junction will undergo band to band tunneling in which the electrons tunnel from the valence band of the n-type tunnel into the conduction band of the p-type and the holes tunnel vice-verse. This results in a leakage current through the gate oxide.
DIBL:Drain induced barrier lowering is related to the reduction in the threshold voltage of the transistor due to the large depletion region created by the Drain potential.U can think of it as-since already a part of the region under the gate is depleted by the drain, only a little amount of gate potential is needed to complete depletion in the rest of the area.This means a lower threshold voltage.
No comments:
Post a Comment