NMOS Pass Transistor Voltages

I have come across several Pass Transistor interview questions on the internet, many of them asking to figure our the final output voltage level. In the past, I have gotten confused with the terminals of a pass transistor because in general, transistors are symmetric and the Source and Drain terminals are interchangeable. Here is my explanation for such a problem so that you don’t ever get confused in case such a question is posed.

B is Vg (V at gate)

X is Vs (V at source)

A is Vd (V at drain)

For an NMOS to conduct, Vgs > Vt, so Node X does not charge beyond a point where Vgs < Vt.

Some sample problems. Assume Vt = 0.7 V. Solve and check solutions at the end of the post.

Most questions asked are variation of the basic serially connected or cascaded NMOS structures. If you stick to the basic principle and solve for each node, you will get your final answer right.

Fig 1: Vx = 4.3 V

Fig 2: Vx = 3 V

Fid 3 (un-named): Va = Vb = Vc =Vo =4.3 V

NMOS and PMOS Operating Regions

Equations that govern the operating region of NMOS and PMOS

NMOS:

Vgs < Vt                                     OFF

Vds < Vgs  -Vt                         LINEAR

Vds > Vgs – Vt                        SATURATION

PMOS

Vsg < |Vt|                                 OFF

Vsd < Vsg – |Vt|                    LINEAR

Vsd > Vsg – |Vt|                    SATURATION

Note: 

1.These equations come handy when analyzing any MOS circuit specially to estimate drain current.

2. The negative scale of PMOS curves.

MOSFET Current Equations and Curves

Note: It is important to remember Id = f(Vgs) in the linear region and Id = f(Vgs^2) in the saturation region

Some common device issues and terminologies

Short Channel Effect: It is the decrease of Vt with the reduction of channel length L

DIBL, Drain Induced Barrier Lowering: As Vds increases, the drain-body depletion region increases and as a result the channel length decreases thus reducing Vt.

Channel Length Modulation: As Vds increases beyond Vd-sat, the saturation point where the surface channel collapses begins to move slightly towards the source, thereby decreasing the effective channel length and decreasing Vt

Why NAND better than NOR

i) PMOS in NAND is in parallel while that in NOR is in series

ii) Parallel PMOS makes a stronger pull up network than serial PMOS

iii) Since hole mobility is lesser than electron mobility, NAND-based design is faster than that of NOR-based design (because of parallel PMOS)

iv) t_phl and t_plh (high to low, low to high times) are more symmetric in NAND than in NOR. t_plh of NOR is slower because of the series PMOS.

PMOS, NMOS Sizing

1. Why is W to L of PMOS is higher than that of NMOS?                         or

2. What are the reasons behind PMOS and NMOS sizing?

Ans: i) PMOS hole mobility is lesser than NMOS electron mobility (approx 1:3)

ii) Since hole mobility is lesser than electron mobility, PMOS width must be greater to compensate and make the pull-up network stronger

iii) If W to L of PMOS is same as the corresponding NMOS, the charging time of the output node would be higher than that of the discharging time (related to NMOS pull-down network)

iv) Sizing is done to maintain equal (or similar) rise and fall times at the output

Note: Usually, W to L to PMOS is 2 or 3 times the W to L of NMOS

Hot Carrier Effect

When carriers (electrons or holes) gain high kinetic energy due to the presence of high electric field within a semiconductor device. Hot electrons are more probable than hot holes since they have higher mobility to begin with. Hot carriers get injected/ trapped in certain areas and cause undesirable device behavior and/or degradation thereby giving rise to Hot Carrier Effects.

In short, Hot Carrier Effect –> Carriers get lodged into the gate oxide —> Vt Variation, Leakage Currents

There are a few types depending upon the location of the hot carrier impact.

1) Drain Avalanche Hot Carrier:

High voltages applied to the drain, cause high fields to be generated near the drain, causing channel carriers to be accelerated into the drain depletion region.
The accelerated carriers collide with the Si atoms in the lattice creating electron-hole pairs some of which may cause further impact ionization. This leads to some carriers lodge into the gate oxide. Over a period of time this leads to variations in Vt.
Injected carriers that do not get trapped in gate oxide make up the gate current. The electron-hole pairs that go into the substrate constitute the substrate current.

2) Channel Hot Electron Injection:

When both gate and drain voltage are high, carriers accelerated toward the drain impinge on on the gate oxide before reaching the drain due to the high gate voltage

3) Substrate Hot Electron Injection:

When substrate bias is high (|Vb| >> 0), the carriers in the substrate are accelerated towards the channel, gain kinetic energy due to the surface field and get lodged into the gate oxide

4) Secondary Generated Hot Electron Injection:

This is similar to (1) where there is secondary electron-hole generation due to impact ionization, this combined with substrate bias, causes the secondary carriers to accelerate towards the surface and hit the gate oxide.


Why Hot Carrier Effect is important?

Device degradation lessens the lifetime of the device – we want a long lifetime.
Contributes to leakage current – we want low power devices

Due to scaling of dimensions but not much reduction is operating voltages, Hot carrier effect is becoming more relevant