1.What is floorplaning?
A. Floor planing is the process of placing Blocks/Macros in the chip/core area, thereby determining the routing areas between them. Floorplan determines the size of die and creates wire tracks for placement of standard cells. It creates power straps and specifies Power Ground(PG) connections. It also determines the I/O pin/pad placement information.
In simple words, Floorplaning is the process of determining the Macro placement, power grid generation and I/O placement.
2. How can you say a floorplan is good?
A. A good floorplaning should meet the following constraints
· Minimize the total chip area
· Make Routing phase easy (Routable)
· Improve the performance by reducing signal delays
3. What are the inputs for floorplan?
A. The following are the inputs for Floorplan
· Synthesized Netlist (.v, .vhdl)\
· Design Constraints (SDC – Synopsys Design Constraints)
· Physical Partitioning Information of the design
· IO Placement file (optional)
· Macro Placement File (optional)
· Floorplaning Control parameters
4. What are the outputs of floorplan?
A. The following are the outputs for floorplan
· Die/Block Area
· I/Os Placed
· Macros placed
· Power Grid Design
· Power Pre-routing
· Standard cell placement areas
5.What are the floorplaning control parameters?
A. Aspect ratio, Core utilization, Row/Core Ratio, Width and eight are the floorplaning control parameters. For more information please visit Floorplaning Control
6. What is the Aspect Ratio?
A. please visit floorplaning control parameters post
7. What is core utilization?
A. please visit floorplaning control parameters post
8. What is total chip utilization?
A. please visit Floorplan control parameters
9. How macro placement is done in floorplaning? or What are the guidelines for macro placement?
A. please visit Macro Placement post
10. What is blockage? What are the different types of blockages? How these blockages are used in physical
design?
A. please visit Blockages and Halos Post
11. What is Halo? How it is useful?
A. Please visit Blockages and Halos Post
12. What are the fly/flight lines? How these fly/flight lines are useful during macroplacement ?
A. Please visit Macro Placement post
13. A netlist consisting of 500k gates and I have to estimate die area and floorplanning. How do I go about it?
A. There are 2 methods to estimate die area
Method 1:
Each cell has got its area according to a specific library. Go through all your cells and multiply each cell in its corresponding area from your vendor's library. Then you can take some density factor - usually for a standard design you should have around 80% density after placement. So from this data you can estimate your
required die area.
Method 2:
One more way of doing it is, Load the design in the implementation tool, try to change the floorplan ( x & y coordinates ) in a such a way that the Starting utilization will be around 50% -to- 60%. Again, it depends on the netlist quality & netlist completion status (like Netlist is 75%, 80% & 90% completed).
14. How to do floor planning for multi Vdd designs?
A. First we have to decide about the power domains, and
add the power rings for each domain, and add the stripes to supply the power for standard cells.
15. How to calculate the power ring width and power straps width and no of power straps using the core power consumption?
A. Please click here for more details
16. What is core utilization percentage?
A. Core utilization percentage indicates the amount of core area used for cell placement. The number is calculated as a ratio of the total cell area (for hard macros and standard cells or soft macro cells) to the core area. A core utilization of 0.8, for example, means that 80% of the core area is used for cell placement and 20
percent is available for routing.
17.When core utilization area increased to 90%, macros got placed outside core area so does it mean that increase in core utilization area decreases width and height?
A. If you go on with 90% then there may be a problem of congestion and routing problem. It means that you can’t do routing within this area. Sometimes you can fit within 90% utilization but while go on for timing optimization like upsize and adding buffers will lead to increase in size. So in this case you can’t do anything so we need to come back to floorplan again. So to be on safer side we are fixing to 70 to 80% utilization.
18. Why do we remove all placed standard cells, and then write out floorplan in DEF format. What's use of DEF file?
A.DEF deals only with floorplan size. So to get the abstract
of the floorplan, we are doing like this. Saving and loading
this file we can get this abstract again. We don’t need to
redo floorplan.
19. Can area recovery be done by downsizing cells at path with positive slack?
A. Yes, Area recovery can be done by downsizing cells at path with positive slack. Also deleting unwanted buffers will also help in area recovery
20. We can manipulate IR drop by changing number of power straps. I increased power straps which reduced IR drop, but how many power straps can I keep adding to reduce IR drop? How to calculate number of straps required. What problems can arise with
increase in number of straps?
A. We can use tools to calculate IR drop (ex:- Voltagestrom, Redhawk) if drop is high. Based on that we can add straps. But if you do projects repeatedly you will come to know that this much straps is enough. In this case you will not need tools. It’s having calculation but it’s not accurate it’s an approximate one. Number of straps will create problem in routing also it affects area. So results will be in routing congestion. To number of power straps required for a design click here.
21. aprPGConnect, is used for logical connection of all VDD, VSS nets of all modules. so how do we connect
all VDD, VSS to global VDD /VSS nets before
placement?
A. The aprPGConnect, is used for logical connection of all
VDD, VSS nets of all modules. For physical connection
A. Floor planing is the process of placing Blocks/Macros in the chip/core area, thereby determining the routing areas between them. Floorplan determines the size of die and creates wire tracks for placement of standard cells. It creates power straps and specifies Power Ground(PG) connections. It also determines the I/O pin/pad placement information.
In simple words, Floorplaning is the process of determining the Macro placement, power grid generation and I/O placement.
2. How can you say a floorplan is good?
A. A good floorplaning should meet the following constraints
· Minimize the total chip area
· Make Routing phase easy (Routable)
· Improve the performance by reducing signal delays
3. What are the inputs for floorplan?
A. The following are the inputs for Floorplan
· Synthesized Netlist (.v, .vhdl)\
· Design Constraints (SDC – Synopsys Design Constraints)
· Physical Partitioning Information of the design
· IO Placement file (optional)
· Macro Placement File (optional)
· Floorplaning Control parameters
4. What are the outputs of floorplan?
A. The following are the outputs for floorplan
· Die/Block Area
· I/Os Placed
· Macros placed
· Power Grid Design
· Power Pre-routing
· Standard cell placement areas
5.What are the floorplaning control parameters?
A. Aspect ratio, Core utilization, Row/Core Ratio, Width and eight are the floorplaning control parameters. For more information please visit Floorplaning Control
6. What is the Aspect Ratio?
A. please visit floorplaning control parameters post
7. What is core utilization?
A. please visit floorplaning control parameters post
8. What is total chip utilization?
A. please visit Floorplan control parameters
9. How macro placement is done in floorplaning? or What are the guidelines for macro placement?
A. please visit Macro Placement post
10. What is blockage? What are the different types of blockages? How these blockages are used in physical
design?
A. please visit Blockages and Halos Post
11. What is Halo? How it is useful?
A. Please visit Blockages and Halos Post
12. What are the fly/flight lines? How these fly/flight lines are useful during macroplacement ?
A. Please visit Macro Placement post
13. A netlist consisting of 500k gates and I have to estimate die area and floorplanning. How do I go about it?
A. There are 2 methods to estimate die area
Method 1:
Each cell has got its area according to a specific library. Go through all your cells and multiply each cell in its corresponding area from your vendor's library. Then you can take some density factor - usually for a standard design you should have around 80% density after placement. So from this data you can estimate your
required die area.
Method 2:
One more way of doing it is, Load the design in the implementation tool, try to change the floorplan ( x & y coordinates ) in a such a way that the Starting utilization will be around 50% -to- 60%. Again, it depends on the netlist quality & netlist completion status (like Netlist is 75%, 80% & 90% completed).
14. How to do floor planning for multi Vdd designs?
A. First we have to decide about the power domains, and
add the power rings for each domain, and add the stripes to supply the power for standard cells.
15. How to calculate the power ring width and power straps width and no of power straps using the core power consumption?
A. Please click here for more details
16. What is core utilization percentage?
A. Core utilization percentage indicates the amount of core area used for cell placement. The number is calculated as a ratio of the total cell area (for hard macros and standard cells or soft macro cells) to the core area. A core utilization of 0.8, for example, means that 80% of the core area is used for cell placement and 20
percent is available for routing.
17.When core utilization area increased to 90%, macros got placed outside core area so does it mean that increase in core utilization area decreases width and height?
A. If you go on with 90% then there may be a problem of congestion and routing problem. It means that you can’t do routing within this area. Sometimes you can fit within 90% utilization but while go on for timing optimization like upsize and adding buffers will lead to increase in size. So in this case you can’t do anything so we need to come back to floorplan again. So to be on safer side we are fixing to 70 to 80% utilization.
18. Why do we remove all placed standard cells, and then write out floorplan in DEF format. What's use of DEF file?
A.DEF deals only with floorplan size. So to get the abstract
of the floorplan, we are doing like this. Saving and loading
this file we can get this abstract again. We don’t need to
redo floorplan.
19. Can area recovery be done by downsizing cells at path with positive slack?
A. Yes, Area recovery can be done by downsizing cells at path with positive slack. Also deleting unwanted buffers will also help in area recovery
20. We can manipulate IR drop by changing number of power straps. I increased power straps which reduced IR drop, but how many power straps can I keep adding to reduce IR drop? How to calculate number of straps required. What problems can arise with
increase in number of straps?
A. We can use tools to calculate IR drop (ex:- Voltagestrom, Redhawk) if drop is high. Based on that we can add straps. But if you do projects repeatedly you will come to know that this much straps is enough. In this case you will not need tools. It’s having calculation but it’s not accurate it’s an approximate one. Number of straps will create problem in routing also it affects area. So results will be in routing congestion. To number of power straps required for a design click here.
21. aprPGConnect, is used for logical connection of all VDD, VSS nets of all modules. so how do we connect
all VDD, VSS to global VDD /VSS nets before
placement?
A. The aprPGConnect, is used for logical connection of all
VDD, VSS nets of all modules. For physical connection
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