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Friday, 10 April 2015

Different types of Physical Cells

Tap Cells (Well Taps): These library cells connect the power and ground connections to the substrate and n­wells, respectively. 
By placing well taps at regular intervals throughout the design, the n­well potential is held constant for proper electrical functioning. The placer places the cells in accordance to the specified distances and automatically snaps them to legal positions (which are the core sites).



Tie Cells : Tie-high and Tie-Low cells are used to connect the gate of the transistor to either power or ground. In Lower technology nodes, if the gate is connected to power/ground the transistor might be turned on/off due to power or ground bounce. These cells are part of standard-cell library. The cells which require Vdd (Typically constant signals tied to 1) connect to Tie high cells The cells which require Vss/Gnd (Typically constant signals tied to 0) connect to Tie Low cells


End Cap Cells : These library cells do not have signal connectivity. They connect only to the power and ground rails once power rails are created in the design. They also ensure that gaps do not occur between the well and implant layers. This prevents DRC violations by satisfying well tie­off requirements for the core rows. Each end of the core row, left and right, can have only one end cap cell specified. 

However, you can specify a list of different end caps for inserting horizontal end cap lines, which terminate the top and bottom boundaries of objects such as macros. A core row can be fragmented (contains gaps), since rows do not intersect objects such as power domains. For this, the tool places end cap cells on both ends of the unfragmented segment.


DeCap Cells : cells are temporary capacitors added in the design between power and ground rails to counter functional failures due to dynamic IR drop.Dynamic I.R. drop happens at the active edge of the clock at which a high percentage of Sequential and Digital elements switch.Due to this simultaneous switching a high current is drawn from the power grid for a small duration.If the power source is far away from a flop the chances are that this flop can go into a metastable state due to IR Drop.To overcome this decaps are added. At an active edge of clock when the current requirement is high , these decaps discharge and provide boost to the power grid. One caveat in usage of decaps is that these add to leakage current. De caps are placed as fillers. The closer they are to the flop’s sequential elements, the better it is. 

Decap cells are typically poly gate transistors where source and drain are connected to the ground rail, and the gate is connected to the power rail. 

when there is an instantaneous switching activity the charge required moves from intrinsic and extrinsic local charge reservoirs as oppose to voltage sources. Extrinsic capacitances are decap cells placed in the design. Intrinsic capacitances are those present naturally in the circuit, such as the grid capacitance, the variable capacitance inside nearby logic, and the neighborhood loading capacitance exposed when the P or N channel are open. 

One drawback of decap cells is that they are very leaky, so the more decap cells the more leakage. Another drawback, which many designers ignore, is the interaction of the decap cells with the package RLC network. Since the die is essentially a capacitor with very small R and L, and the package is a hug RL network, the more decap cells placed the more chance of tuning the circuit into its resonance frequency. That would be trouble, since both VDD and GND will be oscillating. I have seen designs fail because of this Designers typically place decap cells near high activity clock buffers, but I recommend a decap optimization flow where tools study charge requirements at every moment in time and figure out how much decap to place at any node. This should be done while taking package models into account to ensure resonance frequency is not hit







Cells required for Multi-Voltage Design

Special cells are required for implementing a Multi-Voltage design.



1. Level Shifter

2. Isolation Cell

3. Enable Level Shifter

4. Retention Flops

5. Always ON cells

6. Power Gating Switches/MTCMOS switch




Level Shifter: Purpose of this cell is to shift the voltage from low to high as well as high to low. Generally buffer type and Latch type level shifters are available. In general H2L LS's are very simple whereas L2H LS's are little complex and are in general larger in size(double height) and have 2 power pins. There are some placement restrictions for L2H level shifter to handle noise levels in the design. Level shifters are typically used to convert signal levels and protect against sneak leakage paths. With great care, level shifters can be avoided in some cases, but this will become less practicable on a wider scale.






Isolation Cell: These are special cells required at the interface between blocks which are shut-down and always on. They clamp the output node to a known voltage. These cells needs to be placed in an 'always on' region only and the enable signal of the isolation cell needs to be 'always_on'. In a nut-shell, an isolation cell is necessary to isolate floating inputs.

There are 2 types of isolation cells (a) Retain "0″ (b) Retain "1″





Enable Level Shifter: This cell is a combination of a Level Shifter and a Isolation cell.



Retention Flops: These cells are special flops with multiple power supply. They are typically used as a shadow register to retain its value even if the block in which its residing is shut-down. All the paths leading to this register need to be 'always_on' and hence special care must be taken to synthesize/place/route them. In a nut-shell, "When design blocks are switched off for sleep mode, data in all flip-flops contained within the block will be lost. If the designer desires to retain state, retention flip-flops must be used".

The retention flop has the same structure as a standard master-slave flop. However, the retention flop has a balloon latch that is connected to true-Vdd. With the proper series of control signals before sleep, the data in the flop can be written into the balloon latch. Similarly, when the block comes out of sleep, the data can be written back into the flip-flop.




Always ON cells: Generally these are buffers, that remain always powered irrespective of where they are placed. They can be either special cells or regular buffers. If special cells are used, they have thier own secondary power supply and hence can be placed any where in the design. Using regular buffers as Always ON cells restricts the placement of these cells in a specific region.

In a nut-shell, "If data needs to be routed through or from sleep blocks to active blocks and If the routing distance is excessively long or the driving load is excessively large, then buffers might be needed to drive the nets. In these cases, the always-on buffers can be used."





Power Gating Switches/MTCMOS Switch: MTCMOS stands for multi-threshold CMOS, where low-Vt gates are used for speed, and high-Vt gates are used for low leakage. By using high-Vt transistors as header switches, blocks of cells can be switched off to sleep-mode, such that leakage power is greatly reduced. MTCMOS switches can be implemented in various different ways. First, they can be implemented as PMOS (header) or NMOS (footer) switches. Secondly, their granularity can be implemented on a cell-level (fine-grain) or on a block-level (coarse-grain). That is, the switches can be either built into every standard cell, or they can be used to switch off a large design block of standard cells.



Hope this will help you.

Thanks :)

Sample SoC Encounter log File

#######################################################
#                                                     #
#  Encounter Command Logging File                     #
#  Created on Tue Apr 26 14:29:12 2011                #
#                                                     #
#######################################################

#@(#)CDS: Encounter v09.11-s084_1 (32bit) 04/26/2010 12:41 (Linux 2.6)
#@(#)CDS: NanoRoute v09.11-s008 NR100226-1806/USR63-UB (database version 2.30, 93.1.1) {superthreading v1.14}
#@(#)CDS: CeltIC v09.11-s011_1 (32bit) 03/04/2010 09:23:40 (Linux 2.6.9-78.0.25.ELsmp)
#@(#)CDS: CTE 09.11-s016_1 (32bit) Apr  8 2010 03:34:50 (Linux 2.6.9-78.0.25.ELsmp)
#@(#)CDS: CPE v09.11-s023

loadConfig ./encounter.conf
floorPlan -r 1.0 0.6 50 50 50 50
addRing -spacing_bottom 9.9 -width_left 9.9 -width_bottom 9.9 -width_top 9.9 -spacing_top 9.9 -layer_bottom metal1 -width_right 9.9 -around core -center 1 -layer_top metal1 -spacing_right 9.9 -spacing_left 9.9 -layer_right metal2 -layer_left metal2 -offset_top 9.9 -offset_bottom 9.9 -offset_left 9.9 -offset_right 9.9 -nets { gnd vdd }
setPlaceMode -congEffort medium
placeDesign -inPlaceOpt
checkPlace
sroute -noBlockPins -noPadRings
trialRoute
timeDesign -preCTS
setOptMode -yieldEffort none
setOptMode -highEffort
setOptMode -maxDensity 0.95
setOptMode -drcMargin 0.0
setOptMode -holdTargetSlack 0.0 -setupTargetSlack 0.0
setOptMode -noSimplifyNetlist
optDesign -preCTS -drv
createClockTreeSpec -output encounter.cts
specifyClockTree -file encounter.cts
ckSynthesis -rguide cts.rguide -report report.ctsrpt -macromodel report.ctsmdl -fix_added_buffers
trialRoute
timeDesign -postCTS
setExtractRCMode -default -assumeMetFill
extractRC -outfile encounter.cap
setOptMode -yieldEffort none
setOptMode -highEffort
setOptMode -maxDensity 0.95
setOptMode -drcMargin 0.0
setOptMode -holdTargetSlack 0.0 -setupTargetSlack 0.0
setOptMode -noSimplifyNetlist
optDesign -postCTS -hold
optDesign -postCTS -drv
reportClockTree -postRoute -localSkew -report skew.post_troute_local.ctsrpt
addFiller -cell FILL
globalNetConnect vdd -type tiehi
globalNetConnect vdd -type pgpin -pin vdd -all -override
globalNetConnect gnd -type tielo
globalNetConnect gnd -type pgpin -pin gnd -all -override
sroute
globalDetailRoute
setExtractRCMode -engine detail -reduce 0.0
extractRC
setOptMode -yieldEffort none
setOptMode -effort high
setOptMode -maxDensity 0.95
setOptMode -drcMargin 0.0
setOptMode -holdTargetSlack 0.0 -setupTargetSlack 0.0
setOptMode -simplifyNetlist false
setOptMode -usefulSkew false
optDesign -postRoute -incr
addFiller -cell FILL -prefix FIL -fillBoundary
verifyConnectivity -type all -error 1000 -warning 50
verifyGeometry
streamOut final.gds2 -mapFile gds2_encounter.map -outputMacros -stripes 1 -units 1000 -mode ALL
saveNetlist -excludeLeafCell final.v
rcOut -spf final.dspf
selectInst U23
fit
loadConfig ./encounter.conf
floorPlan -r 1.0 0.6 50 50 50 50
addRing -spacing_bottom 9.9 -width_left 9.9 -width_bottom 9.9 -width_top 9.9 -spacing_top 9.9 -layer_bottom metal1 -width_right 9.9 -around core -center 1 -layer_top metal1 -spacing_right 9.9 -spacing_left 9.9 -layer_right metal2 -layer_left metal2 -offset_top 9.9 -offset_bottom 9.9 -offset_left 9.9 -offset_right 9.9 -nets { gnd vdd }
setPlaceMode -congEffort medium
placeDesign -inPlaceOpt
checkPlace
sroute -noBlockPins -noPadRings
trialRoute
timeDesign -preCTS
setOptMode -yieldEffort none
setOptMode -highEffort
setOptMode -maxDensity 0.95
setOptMode -drcMargin 0.0
setOptMode -holdTargetSlack 0.0 -setupTargetSlack 0.0
setOptMode -noSimplifyNetlist
optDesign -preCTS -drv
createClockTreeSpec -output encounter.cts
specifyClockTree -file encounter.cts
ckSynthesis -rguide cts.rguide -report report.ctsrpt -macromodel report.ctsmdl -fix_added_buffers
trialRoute
timeDesign -postCTS
setExtractRCMode -default -assumeMetFill
extractRC -outfile encounter.cap
setOptMode -yieldEffort none
setOptMode -highEffort
setOptMode -maxDensity 0.95
setOptMode -drcMargin 0.0
setOptMode -holdTargetSlack 0.0 -setupTargetSlack 0.0
setOptMode -noSimplifyNetlist
optDesign -postCTS -hold
optDesign -postCTS -drv
reportClockTree -postRoute -localSkew -report skew.post_troute_local.ctsrpt
addFiller -cell FILL
globalNetConnect vdd -type tiehi
globalNetConnect vdd -type pgpin -pin vdd -all -override
globalNetConnect gnd -type tielo
globalNetConnect gnd -type pgpin -pin gnd -all -override
sroute
globalDetailRoute
setExtractRCMode -engine detail -reduce 0.0
extractRC
setOptMode -yieldEffort none
setOptMode -effort high
setOptMode -maxDensity 0.95
setOptMode -drcMargin 0.0
setOptMode -holdTargetSlack 0.0 -setupTargetSlack 0.0
setOptMode -simplifyNetlist false
setOptMode -usefulSkew false
optDesign -postRoute -incr
addFiller -cell FILL -prefix FIL -fillBoundary
verifyConnectivity -type all -error 1000 -warning 50
verifyGeometry
streamOut final.gds2 -mapFile gds2_encounter.map -outputMacros -stripes 1 -units 1000 -mode ALL
saveNetlist -excludeLeafCell final.v
rcOut -spf final.dspf
panPage 0 1
panPage 0 -1
panPage 1 0
panPage -1 0
fit
loadConfig ./encounter.conf
floorPlan -r 1.0 0.6 50 50 50 50
addRing -spacing_bottom 9.9 -width_left 9.9 -width_bottom 9.9 -width_top 9.9 -spacing_top 9.9 -layer_bottom metal1 -width_right 9.9 -around core -center 1 -layer_top metal1 -spacing_right 9.9 -spacing_left 9.9 -layer_right metal2 -layer_left metal2 -offset_top 9.9 -offset_bottom 9.9 -offset_left 9.9 -offset_right 9.9 -nets { gnd vdd }
setPlaceMode -congEffort medium
placeDesign -inPlaceOpt
checkPlace
sroute -noBlockPins -noPadRings
trialRoute
timeDesign -preCTS
setOptMode -yieldEffort none
setOptMode -highEffort
setOptMode -maxDensity 0.95
setOptMode -drcMargin 0.0
setOptMode -holdTargetSlack 0.0 -setupTargetSlack 0.0
setOptMode -noSimplifyNetlist
optDesign -preCTS -drv
createClockTreeSpec -output encounter.cts
specifyClockTree -file encounter.cts
ckSynthesis -rguide cts.rguide -report report.ctsrpt -macromodel report.ctsmdl -fix_added_buffers
trialRoute
timeDesign -postCTS
setExtractRCMode -default -assumeMetFill
extractRC -outfile encounter.cap
setOptMode -yieldEffort none
setOptMode -highEffort
setOptMode -maxDensity 0.95
setOptMode -drcMargin 0.0
setOptMode -holdTargetSlack 0.0 -setupTargetSlack 0.0
setOptMode -noSimplifyNetlist
optDesign -postCTS -hold
optDesign -postCTS -drv
reportClockTree -postRoute -localSkew -report skew.post_troute_local.ctsrpt
addFiller -cell FILL
globalNetConnect vdd -type tiehi
globalNetConnect vdd -type pgpin -pin vdd -all -override
globalNetConnect gnd -type tielo
globalNetConnect gnd -type pgpin -pin gnd -all -override
sroute
globalDetailRoute
setExtractRCMode -engine detail -reduce 0.0
extractRC
setOptMode -yieldEffort none
setOptMode -effort high
setOptMode -maxDensity 0.95
setOptMode -drcMargin 0.0
setOptMode -holdTargetSlack 0.0 -setupTargetSlack 0.0
setOptMode -simplifyNetlist false
setOptMode -usefulSkew false
optDesign -postRoute -incr
addFiller -cell FILL -prefix FIL -fillBoundary
verifyConnectivity -type all -error 1000 -warning 50
verifyGeometry
streamOut final.gds2 -mapFile gds2_encounter.map -outputMacros -stripes 1 -units 1000 -mode ALL
saveNetlist -excludeLeafCell final.v
rcOut -spf final.dspf
fit
selectInst U14
loadConfig ./encounter.conf
floorPlan -r 1.0 0.6 50 50 50 50
addRing -spacing_bottom 9.9 -width_left 9.9 -width_bottom 9.9 -width_top 9.9 -spacing_top 9.9 -layer_bottom metal1 -width_right 9.9 -around core -center 1 -layer_top metal1 -spacing_right 9.9 -spacing_left 9.9 -layer_right metal2 -layer_left metal2 -offset_top 9.9 -offset_bottom 9.9 -offset_left 9.9 -offset_right 9.9 -nets { gnd vdd }
setPlaceMode -congEffort medium
placeDesign -inPlaceOpt
checkPlace
sroute -noBlockPins -noPadRings
trialRoute
timeDesign -preCTS
setOptMode -yieldEffort none
setOptMode -highEffort
setOptMode -maxDensity 0.95
setOptMode -drcMargin 0.0
setOptMode -holdTargetSlack 0.0 -setupTargetSlack 0.0
setOptMode -noSimplifyNetlist
optDesign -preCTS -drv
createClockTreeSpec -output encounter.cts
specifyClockTree -file encounter.cts
ckSynthesis -rguide cts.rguide -report report.ctsrpt -macromodel report.ctsmdl -fix_added_buffers
trialRoute
timeDesign -postCTS
setExtractRCMode -default -assumeMetFill
extractRC -outfile encounter.cap
setOptMode -yieldEffort none
setOptMode -highEffort
setOptMode -maxDensity 0.95
setOptMode -drcMargin 0.0
setOptMode -holdTargetSlack 0.0 -setupTargetSlack 0.0
setOptMode -noSimplifyNetlist
optDesign -postCTS -hold
optDesign -postCTS -drv
reportClockTree -postRoute -localSkew -report skew.post_troute_local.ctsrpt
addFiller -cell FILL
globalNetConnect vdd -type tiehi
globalNetConnect vdd -type pgpin -pin vdd -all -override
globalNetConnect gnd -type tielo
globalNetConnect gnd -type pgpin -pin gnd -all -override
sroute
globalDetailRoute
setExtractRCMode -engine detail -reduce 0.0
extractRC
setOptMode -yieldEffort none
setOptMode -effort high
setOptMode -maxDensity 0.95
setOptMode -drcMargin 0.0
setOptMode -holdTargetSlack 0.0 -setupTargetSlack 0.0
setOptMode -simplifyNetlist false
setOptMode -usefulSkew false
optDesign -postRoute -incr
addFiller -cell FILL -prefix FIL -fillBoundary
verifyConnectivity -type all -error 1000 -warning 50
verifyGeometry
streamOut final.gds2 -mapFile gds2_encounter.map -outputMacros -stripes 1 -units 1000 -mode ALL
saveNetlist -excludeLeafCell final.v
rcOut -spf final.dspf
fit
selectInst U17
deselectAll
selectInst U16
deselectAll
selectInst U3
deselectAll
selectInst U23
deselectAll
selectInst U3
deselectAll
selectInst U15
deselectAll
selectInst U3
deselectAll
selectInst U15
deselectAll
selectInst U1
deselectAll
selectInst U2
loadConfig ./encounter.conf
floorPlan -r 1.0 0.6 50 50 50 50
addRing -spacing_bottom 9.9 -width_left 9.9 -width_bottom 9.9 -width_top 9.9 -spacing_top 9.9 -layer_bottom metal1 -width_right 9.9 -around core -center 1 -layer_top metal1 -spacing_right 9.9 -spacing_left 9.9 -layer_right metal2 -layer_left metal2 -offset_top 9.9 -offset_bottom 9.9 -offset_left 9.9 -offset_right 9.9 -nets { gnd vdd }
setPlaceMode -congEffort medium
placeDesign -inPlaceOpt
checkPlace
sroute -noBlockPins -noPadRings
trialRoute
timeDesign -preCTS
setOptMode -yieldEffort none
setOptMode -highEffort
setOptMode -maxDensity 0.95
setOptMode -drcMargin 0.0
setOptMode -holdTargetSlack 0.0 -setupTargetSlack 0.0
setOptMode -noSimplifyNetlist
optDesign -preCTS -drv
createClockTreeSpec -output encounter.cts
specifyClockTree -file encounter.cts
ckSynthesis -rguide cts.rguide -report report.ctsrpt -macromodel report.ctsmdl -fix_added_buffers
trialRoute
timeDesign -postCTS
setExtractRCMode -default -assumeMetFill
extractRC -outfile encounter.cap
setOptMode -yieldEffort none
setOptMode -highEffort
setOptMode -maxDensity 0.95
setOptMode -drcMargin 0.0
setOptMode -holdTargetSlack 0.0 -setupTargetSlack 0.0
setOptMode -noSimplifyNetlist
optDesign -postCTS -hold
optDesign -postCTS -drv
reportClockTree -postRoute -localSkew -report skew.post_troute_local.ctsrpt
addFiller -cell FILL
globalNetConnect vdd -type tiehi
globalNetConnect vdd -type pgpin -pin vdd -all -override
globalNetConnect gnd -type tielo
globalNetConnect gnd -type pgpin -pin gnd -all -override
sroute
globalDetailRoute
setExtractRCMode -engine detail -reduce 0.0
extractRC
setOptMode -yieldEffort none
setOptMode -effort high
setOptMode -maxDensity 0.95
setOptMode -drcMargin 0.0
setOptMode -holdTargetSlack 0.0 -setupTargetSlack 0.0
setOptMode -simplifyNetlist false
setOptMode -usefulSkew false
optDesign -postRoute -incr
addFiller -cell FILL -prefix FIL -fillBoundary
verifyConnectivity -type all -error 1000 -warning 50
verifyGeometry
streamOut final.gds2 -mapFile gds2_encounter.map -outputMacros -stripes 1 -units 1000 -mode ALL
saveNetlist -excludeLeafCell final.v
rcOut -spf final.dspf
loadConfig ./encounter.conf
floorPlan -r 1.0 0.6 50 50 50 50
addRing -spacing_bottom 9.9 -width_left 9.9 -width_bottom 9.9 -width_top 9.9 -spacing_top 9.9 -layer_bottom metal1 -width_right 9.9 -around core -center 1 -layer_top metal1 -spacing_right 9.9 -spacing_left 9.9 -layer_right metal2 -layer_left metal2 -offset_top 9.9 -offset_bottom 9.9 -offset_left 9.9 -offset_right 9.9 -nets { gnd vdd }
setPlaceMode -congEffort medium
placeDesign -inPlaceOpt
checkPlace
sroute -noBlockPins -noPadRings
trialRoute
timeDesign -preCTS
setOptMode -yieldEffort none
setOptMode -highEffort
setOptMode -maxDensity 0.95
setOptMode -drcMargin 0.0
setOptMode -holdTargetSlack 0.0 -setupTargetSlack 0.0
setOptMode -noSimplifyNetlist
optDesign -preCTS -drv
createClockTreeSpec -output encounter.cts
specifyClockTree -file encounter.cts
ckSynthesis -rguide cts.rguide -report report.ctsrpt -macromodel report.ctsmdl -fix_added_buffers
trialRoute
timeDesign -postCTS
setExtractRCMode -default -assumeMetFill
extractRC -outfile encounter.cap
setOptMode -yieldEffort none
setOptMode -highEffort
setOptMode -maxDensity 0.95
setOptMode -drcMargin 0.0
setOptMode -holdTargetSlack 0.0 -setupTargetSlack 0.0
setOptMode -noSimplifyNetlist
optDesign -postCTS -hold
optDesign -postCTS -drv
reportClockTree -postRoute -localSkew -report skew.post_troute_local.ctsrpt
addFiller -cell FILL
globalNetConnect vdd -type tiehi
globalNetConnect vdd -type pgpin -pin vdd -all -override
globalNetConnect gnd -type tielo
globalNetConnect gnd -type pgpin -pin gnd -all -override
sroute
globalDetailRoute
setExtractRCMode -engine detail -reduce 0.0
extractRC
setOptMode -yieldEffort none
setOptMode -effort high
setOptMode -maxDensity 0.95
setOptMode -drcMargin 0.0
setOptMode -holdTargetSlack 0.0 -setupTargetSlack 0.0
setOptMode -simplifyNetlist false
setOptMode -usefulSkew false
optDesign -postRoute -incr
addFiller -cell FILL -prefix FIL -fillBoundary
verifyConnectivity -type all -error 1000 -warning 50
verifyGeometry
streamOut final.gds2 -mapFile gds2_encounter.map -outputMacros -stripes 1 -units 1000 -mode ALL
saveNetlist -excludeLeafCell final.v
rcOut -spf final.dspf
fit
selectInst U23
deselectAll
selectInst U3
deselectAll
selectInst U14
deselectAll
selectInst U22
deselectAll
selectInst U20
deselectAll
selectInst U22
deselectAll
selectInst U21
deselectAll
selectInst U20
deselectAll
selectInst U3

Tuesday, 7 April 2015

NMOS Pass Transistor Voltages

I have come across several Pass Transistor interview questions on the internet, many of them asking to figure our the final output voltage level. In the past, I have gotten confused with the terminals of a pass transistor because in general, transistors are symmetric and the Source and Drain terminals are interchangeable. Here is my explanation for such a problem so that you don’t ever get confused in case such a question is posed.


B is Vg (V at gate)
X is Vs (V at source)
A is Vd (V at drain)
For an NMOS to conduct, Vgs > Vt, so Node X does not charge beyond a point where Vgs < Vt.
Some sample problems. Assume Vt = 0.7 V. Solve and check solutions at the end of the post.




Most questions asked are variation of the basic serially connected or cascaded NMOS structures. If you stick to the basic principle and solve for each node, you will get your final answer right.

Fig 1: Vx = 4.3 V
Fig 2: Vx = 3 V
Fid 3 (un-named): Va = Vb = Vc =Vo =4.3 V

NMOS and PMOS Operating Regions

Equations that govern the operating region of NMOS and PMOS


NMOS:
Vgs < Vt                                     OFF
Vds < Vgs  -Vt                         LINEAR
Vds > Vgs – Vt                        SATURATION


PMOS
Vsg < |Vt|                                 OFF
Vsd < Vsg – |Vt|                    LINEAR
Vsd > Vsg – |Vt|                    SATURATION


Note: 
1.These equations come handy when analyzing any MOS circuit specially to estimate drain current.
2. The negative scale of PMOS curves.



MOSFET Current Equations and Curves

Note: It is important to remember Id = f(Vgs) in the linear region and Id = f(Vgs^2) in the saturation region

Some common device issues and terminologies

Short Channel Effect: It is the decrease of Vt with the reduction of channel length L
DIBL, Drain Induced Barrier Lowering: As Vds increases, the drain-body depletion region increases and as a result the channel length decreases thus reducing Vt.
Channel Length Modulation: As Vds increases beyond Vd-sat, the saturation point where the surface channel collapses begins to move slightly towards the source, thereby decreasing the effective channel length and decreasing Vt

Why NAND better than NOR


i) PMOS in NAND is in parallel while that in NOR is in series

ii) Parallel PMOS makes a stronger pull up network than serial PMOS

iii) Since hole mobility is lesser than electron mobility, NAND-based design is faster than that of NOR-based design (because of parallel PMOS)

iv) t_phl and t_plh (high to low, low to high times) are more symmetric in NAND than in NOR. t_plh of NOR is slower because of the series PMOS.

PMOS, NMOS Sizing

1. Why is W to L of PMOS is higher than that of NMOS?                         or
2. What are the reasons behind PMOS and NMOS sizing?
Ans: i) PMOS hole mobility is lesser than NMOS electron mobility (approx 1:3)
ii) Since hole mobility is lesser than electron mobility, PMOS width must be greater to compensate and make the pull-up network stronger
iii) If W to L of PMOS is same as the corresponding NMOS, the charging time of the output node would be higher than that of the discharging time (related to NMOS pull-down network)
iv) Sizing is done to maintain equal (or similar) rise and fall times at the output
Note: Usually, W to L to PMOS is 2 or 3 times the W to L of NMOS

Hot Carrier Effect

When carriers (electrons or holes) gain high kinetic energy due to the presence of high electric field within a semiconductor device. Hot electrons are more probable than hot holes since they have higher mobility to begin with. Hot carriers get injected/ trapped in certain areas and cause undesirable device behavior and/or degradation thereby giving rise to Hot Carrier Effects.

In short, Hot Carrier Effect –> Carriers get lodged into the gate oxide —> Vt Variation, Leakage Currents

There are a few types depending upon the location of the hot carrier impact.

1) Drain Avalanche Hot Carrier:

High voltages applied to the drain, cause high fields to be generated near the drain, causing channel carriers to be accelerated into the drain depletion region.
The accelerated carriers collide with the Si atoms in the lattice creating electron-hole pairs some of which may cause further impact ionization. This leads to some carriers lodge into the gate oxide. Over a period of time this leads to variations in Vt.
Injected carriers that do not get trapped in gate oxide make up the gate current. The electron-hole pairs that go into the substrate constitute the substrate current.

2) Channel Hot Electron Injection:

When both gate and drain voltage are high, carriers accelerated toward the drain impinge on on the gate oxide before reaching the drain due to the high gate voltage

3) Substrate Hot Electron Injection:

When substrate bias is high (|Vb| >> 0), the carriers in the substrate are accelerated towards the channel, gain kinetic energy due to the surface field and get lodged into the gate oxide

4) Secondary Generated Hot Electron Injection:

This is similar to (1) where there is secondary electron-hole generation due to impact ionization, this combined with substrate bias, causes the secondary carriers to accelerate towards the surface and hit the gate oxide.


Why Hot Carrier Effect is important?

Device degradation lessens the lifetime of the device – we want a long lifetime.
Contributes to leakage current – we want low power devices

Due to scaling of dimensions but not much reduction is operating voltages, Hot carrier effect is becoming more relevant

Leakage Currents in MOSFETS

Here is a figure that shows the different leakage currents in a MOSFET (Useful Picture)


Interconnect Delay Reduction Using Buffer Insertion

Ever wondered how the propagation delay of an interconnect is reduced by inserting buffers in between? Here is an explanation.



Latchup – Cause, Effect and Prevention



Here is a typical Bulk CMOS device (a simple Inverter)



Now, here is the same figure showing the parasitic BJTs that cause latchup.


Short Circuit Power

When dynamic power is analyzed the switching component of power consumption, an instantaneous rise time was assumed, which insures that only one of the transistors is ON. In practice, finite rise and fall times results in a direct current path between the supply and ground, GND, this exists for a short period of time during switching.


 
Short circuit power [3]
Consider an example of inverter. During switching both NMOS and PMOS transistors in the circuit conduct simultaneously for a short amount of time. Specifically, when the condition, VTn (lesser than) Vin (lesser than) Vdd - |VTp| holds for the input voltage, where VTn and VTp are NMOS and PMOS thresholds, there will be a conductive path open between Vdd and GND because both the NMOS and PMOS devices will be simultaneously on. This forms direct current path between the power supply and the ground. This current has no contribution towards charging of the output capacitance of the logic gate.

When the input rising voltage exceeds the threshold voltage of NMOS transistor, it starts conducting. Similarly until input voltage reaches Vdd-|Vt,p| PMOS transistor remains ON. Thus for some time both transistors are ON. Similar event causes short circuit current to flow when signal is falling. Short circuit current terminates when transition is completed.

Assuming symmetric inverter with Kn=Kp=K and Vt,n=|Vt,p|=Vt and very small capacitive load and both rise and fall times are same we can write,
Pavg(short circuit) = 1/12.k.τ.Fclk.(Vdd-2Vt)3 [1]

Thus short circuit power is directly proportional to rise time, fall time and k. Therefore reducing the input transition times will decrease the short circuit current component. But propagation delay requirements have to be considered while doing so.

Short circuit currents are significant when the rise/fall time at the input of a gate is much larger than the output rise/ fall time. This is because the short-circuit path will be active for a longer period of time. To minimize the total average short-circuits current, it is desirable to have equal input and output edge times [2]. In this case, the power consumed by the short-circuit currents is typically less than 10% of the total dynamic power. An important point to note is that if the supply is lowered to be below the sum of the thresholds of the transistors, Vdd (lesser than) VTn + |VTp|, the short-circuit currents can be eliminated because both devices will not be on at the same time for any value of input voltage.

References
[1] Sung Mo Kang and Yusuf Leblebici, “CMOS Digital Integrated Circuits-Analysis and Design”, Tata McGraw Hill, Third Edition, New Delhi, 2003

[2] Anantha P. Chandrakasan, Samuel Sheng and Robert W.Broadersen, “Low Power CMOS Digital Design”, IEEE Journal of Solid State Circuits, vol. 27, no. 4, pp. 472-484, April 1992

[3] Michael Keating, David Flynn, Robert Aitken, Alan Gibsons and Kaijian Shi, “Low Power Methodology Manual for System on Chip Design”, Springer Publications, NewYork, 2007, www.lpmm-book.org, 4/9/2007