Timing arcs

What is a timing arc: Static timing analysis works on the concept of timing paths. Each path starts from either primary input or a register and ends at a primary input or register. In-between, the path traverses through what are known as timing arcs. In other words, we can say that timing arc is a component of a timing path. We can define a timing arc as an indivisible path from one pin to another and tells EDA tool to consider the path between the pins. For instance, AND, NAND, NOT, full adder cell etc. gates have arcs from each input pin to each output pin. Also, sequential cells such as flops and latches have arcs from clock pin to output pins and data pins.

Figure 1 : Figure showing cell and net arcs

      Terminology: The common terminology related to timing arcs is as follows:

• Source pin: The pin from which timing arc originates (pin IN1 and IN2 in figure1)
• Sink pin: The pin at which timing arc ends (pin OUT in figure2)

 

Types of arcs: Timing arcs can be categorized into two categories – cell arcs and net arcs.

• ·         Cell arcs: These are between an input pin and output pin of a cell. In other words, source pin is an input pin of a cell and sink pin is an output pin of a cell. In the figure shown above, arcs (IN1 -> OUT) and (IN2 -> OUT) are cell arcs. Cell arcs are further divided into sequential and combinational arcs as discussed below.
   
• ·      Net arcs: These arcs are between driver pin of a net and load pin of a net. In other words, source pin is an output pin of one cell and sink pin is an input pin of another cell. In the figure shown above, arc (OUT -> IN2) is a net arc.

 

Sequential and combinational arcs: As discussed above, cells are can be sequential or combinational. Sequential arcs are between the clock pin of a sequential cell and either input or output pin. Setup and hold arcs are between input data pin and clock pin. Sequential delay arc is between clock pin and output pin of sequential elements. On the other hand, combinational arcs are between an input data and output data pin of a combinational cell or block.

Information contained in timing arc: A timing arc provides following information:

     i)   If the path can be traversed through pin1 to pin2. If the path can be traversed, we say that an arc exists between pin1 and pin2.

     ii)      Under what condition the path will be traversed, known as ‘sdf condition’ 

     iii)     What time it takes from the source pin to the destination pin of the arc to traverse in the path       

      iv)     Timing sense of the arc as explained below

Timing sense: Timing sense of an arc is defined as the sense of traversal from source pin of the timing arc to the sink pin of the timing arc. Timing sense can be ‘positive unate’, ‘negative unate’ and ‘non-unate’.

     ->  Positive unate arc: An arc is said to be positive unite if rise transition at the source pin causes rise transition at sink pin and vice-versa.  Cells of type AND, OR gate etc. have positive unate arcs. All net arcs are positive unate arcs.

     -> Negative unate arc: An arc is said to be negative unite if rise transition at the source pin causes fall transition at the sink pin and vice-versa. NAND, NOR and Inverter have negative unate arcs.

     -> Non unate arcs: If there is no such relationship between the source and sink pins of a timing arc, the arc is said to be non-unate. XOR gate has non-unate timing arcs.

From what source timing arcs are picked: For cell arcs, the existence of arc is picked from liberty files. The cell has a function defined that identifies if the arc is there from its input (say ‘x’) to output (say ‘y’). in most of the cases, the value of the arc is also picked from liberty, but in case you have read SDF, it is picked from SDF (Standard Delay Format) file. On the other hand, for net arcs, the existence of arc is picked from connectivity information (netlist). The net arcs are calculated based on the parasitic values given in SPEF (Standard Parasitics Exchange Format) file, or SDF (like in case above).

Importance of timing arcs: Timing arcs have a very important role in VLSI design industry. Whole of the optimization process right from gate level netlist till final signoff revolves around timing arcs. The presence of correct timing arcs in liberty file is very essential for high quality signoff or there may not be correlation between simulation and silicon).