PD Interview questions

Physical design interview questions

what all inputs to the design

Logical library

SDC,

Netlist.

Physical library,

Technology file,

Tlu+ files

2.      what is in logical libraries

timing & functional information.

3.      how are values comming into logical libraries

from .lib

4.      what are sdcs, how do u decide that a path is a false path?

Sdc

Design rule checks, environmental constraint: pvt disable arcs, false paths, multicycle paths

Optimization constraints: area, power & timing.

5.      what is max transition? how you decide that value?

Wherw the slew is worst. Based on top levwl guys experience i.e 20% for data and 10%for  clock.

6.      How do u set max output load (based on what factors?)

The max_capacitance value can vary with the operating frequency of a cell. (Because the capacitive load vary as per relationship of Xc=1/ωC .)

7.      What are the inputs to PT?

Sdc, netlist,

8.      How did u do power planning?

9.      How did u decide metal 5 straps?

    Based on IR drop.

10.  Are there in vias between metal 5 and metal 1?

11.  Given two configuration of Vdd and Vss; 1. VDD VDD VSS VSS 2. VDD VSS VDD VSS..........which configuration you have used and what does the tool prefer?

Vdd vss because alternative (VDD VSS) will offer better routing resources.

12.  Why u require uncertainity before cts with ideal clock?

At pre CTS stage uncertainty is combination of skew, jitter and margin.

To get the better timing at pre CTS.

16. I said -for presenting worst case for setup analysis : then he said he can increase the operating frequency, then y uncertainity is required?

17. What are NDR rules, clock shielding, which metal layer?

Shielding

Double space

 double width

top metal layers after power distribution layers.

Because after power clock is the main power hungry.

18. What does u do for low power design?

We apply low power techniques.

Clock gating

Multiple Vt libraries

Multi voltage design

Power gating.

19. What are retention registers?

Retention flops are used in power gating.

To retain the position of the off block when it is turned in.

20. what are HVT cells, how area increases with HVT cells?

For HVT cells the oxide thickness under gate is very high. Such that it can reduces the leakage current. (as oxide thickness increases little area increases)

21. What does CTS do for routing clocks? Global routing..?

22. How global routing is different from detailed routing?

Global routing is first stage of routing which checks for routing congestion of the device.

In track assignment real metal traces are connected to std cells.

23. How GR will handle congested paths, what is its impact on delay?

24. What is single case, worst case and best case and OCV analysis?

25. How can one library have many values for same input slew and output load?

26. What is CRPR? Explain?

27. Logic Design - Difference between flip flops n latch?

28. Convert D into T

29. Get inverter using XOR

Tie one of the input to vdd(logic one).

Now it will work as a inverter.

30. Will you give constraints for via in CTS or not. How vias will effect the clock routing?      

Person2:

2.  In floorplan what all the factor you have to consider?defining core areas

Perphery area io ports power ports corner cells filler cells

macro placement

Placement blockages

Power network synthesis.

3. Consider you have two macros placed next to each other, what is minimum spacing between the macros?

4. (extension on Q3) u cant over draw any metal layer on the macros and u have macro pins facing the narrow region, what should be the minimum spacing between the macros?
5. What does SDC consist of?

6. How to resolve setup/hold violation after post CTS?

Setup : by lowering the freq

Hold by: working at lowering temperatures.

7. What metal layer you will use for clock routing and why? (top most layer in design is metal7)metal 4 and 5.
8. Useful skew?

9. Cross talk? How to take care of it?
10. Congestion (placement and routing)?
11. Why we will give virtual clock while setting input delay?

Person 3:

1. tell me about torpedo, technology, foundry, clk freq, no. of clk, no of std cells, metal layers, WNS TNS

2. Was your design setup and hold clean  if not y?

3. what is setup and hold, what is slack

4. diff latch and ff which has more delay

5. what is SPEF?

6. Measures u took to fix setup and hold?

7. drew buff using xor 

8. what is mux ?

9. explain clock gating?

10. in PD flow which was most challenging

11. explain cross talk?

12. explain electronmigration?

13. what isAntenna ratio?

14. how will u reduce IR drop?

15. Given 1000 Hard macros how will u floor plan ?

16. why clock uses NDR.?

Person3:

1. tell me about torpedo, technology, foundry, clk freq, no. of clk, no of std cells, metal layers, WNS TNS

2. was ur design setup and hold clean  if not y?

3. what is setup and hold, what is slack

4. diff latch and ff which has more delay

5. what u did in CTS (input files)?

6. Measures u took to fix setup and hold.

7. modes and corners?

8. design a 5x1 mux using 2x1 mux

9. how slew is related to drive strength and delay?

10. in PD flow which was most challenging?

11. cross talk reduction techniques?

12. hold fixing for reg to out path?

13. WC_BC analysis and OCV?

14. how will u reduce IR drop?

15. how u placed ur macros? 

16. why clock uses NDR.

17.difference between LVT and HVT cells?

18. how to convert a T flip flop to get same output as input Dff?

Person4:

2)Same design for everyone 
3)inputs to your design
4)What are the content of. Lib file..
5)difference b/w normal buff n clkbuf 
6)Cross talk 
7)What happens if we use cel view instead of fram view.
8)What gate to prefer for clock generation..
8)Congestion n how to overcome 
9)How much run time for cts 
10)How much time it'll take now
11)Buffer using xor 
12)17:1 mux using 2:1 mux 
13)Constraints for cts
14)macro placement in floorplan stage
15)Spacing b/w macro

                                                     No of pins x metal pitch
Distance between the macros = -------------------------------
                                                    (no of metal layers used /2)
16)driving point in your design, data or clock..
17)How Clock uncertainty was introduced
18)How vt of cell is determined 
19)Which vt cell to use for hold fixing
20)ndr 
21)via b/w m5 n m1..
22)low power design
23)diff b/w latch n ff 
24)if 2ns clk is given at high level of 10ns,what is the o/p

Person5:

1)tell me abt yourself 

2)what are factor affecting vt 

3)how saturation region is different from other two

4)in wt region transistor act as amplifier 

5)how do u covert jk to d flip flop?

6)how to obtain inverter from nand 

7)explain asic flow ?

8)what are all inputs u 've given to ur design ? inputs at each stage ?

10)what is OCV explain ?

11)inputs  given to pt_shell

12)what is .db and lef contains ?

13)how do you give accurate delays to pt_shell , wire load models defined in lib are not accurate ?

14)how to reduce propagation delay ?

15)explain floor plan ?

16)explain placement ?

16)if i 've oly 20 setup violations because of few standard cells and i don wanna go back to floorplan at all wt will be the next thing to do ?

17)after cts what is the next step explain ?

18) if u ve global routing congestion at standard cells how do u reduce it ?

19) layers used in torpedo ?

20)why metal 6 is used t top and why metal 1 is used to prerout ?

21)different path group in your design ?

22)drc to check in pd flow ?

23) is there any inter clock domain in your design?  

24)what are all physical drc's ?

25)next step after routing explain ?

26)if i ve critical path due to standard cell how do u reduce after placement ?

27)wr do use separate tool to check lvs ?

28)what is the effect of EM ?

29)can i make skew zero if so what will be the effect ? is there any skew target to ua design?

30)how do u set uncertainity for interclock domain path ?

31)what are all the low power techniques u aware of ?

32)how do you decide location of ports?

33)What are retention registers?

34)explain me negative and positive skew and how r they decided while optimization
 these are the questions for which i ve answered sm thing  and i forgot few questions 



Interview Questions!!

1. * What is signal integrity? How it affects Timing?
2. * What is IR drop? How to avoid .how it affects timing?
3. * What is EM and it effects?
4. * What is floor plan and power plan?
5. * What are types of routing?
6. * What is a grid .why we need and different types of grids?
7. * What is core and how u will decide w/h ratio for core?
8. * What is effective utilization and chip utilization?
9. * What is latency? Give the types?
10. * What is LEF?
11. * What is DEF?
12. * What are the steps involved in designing an optimal pad ring?
13. * What are the steps that you have done in the design flow?
14. * What are the issues in floor plan?
15. * How can you estimate area of block?
16. * How much aspect ratio should be kept (or have you kept) and what is the utilization?
17. * How to calculate core ring and stripe widths?
18. * What if hot spot found in some area of block? How you tackle this?
19. * After adding stripes also if you have hot spot what to do?
20. * What is threshold voltage? How it affect timing?
21. * What is content of lib, lef, sdc?
22. * What is meant my 9 track, 12 track standard cells?
23. * What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
24. * What is setup and hold? Why there are ? What if setup and hold violates?
25. * In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum operating frequency?
26. * How R and C values are affecting time?
27. * How ohm (R), fared (C) is related to second (T)?
28. * What is transition? What if transition time is more?
29. * What is difference between normal buffer and clock buffer?
30. * What is antenna effect? How it is avoided?
31. * What is ESD?
32. * What is cross talk? How can you avoid?
33. * How double spacing will avoid cross talk?
34. * What is difference between HFN synthesis and CTS?
35. * What is hold problem? How can you avoid it?
36. * For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select? Why?
37. * What is partial floor plan?
38. * What parameters (or aspects) differentiate Chip Design & Block level design??
39. * How do you place macros in a full chip design?
40. * Differentiate between a Hierarchical Design and flat design?
41. * Which is more complicated when u have a 48 MHz and 500 MHz clock design?
42. * Name few tools which you used for physical verification?
43. * What are the input files will you give for primetime correlation?
44. * What are the algorithms used while routing? Will it optimize wire length?
45. * How will you decide the Pin location in block level design?
46. * If the routing congestion exists between two macros, then what will you do?
47. * How will you place the macros?
48. * How will you decide the die size?
49. * If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?
50. * If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?
51. * In your project what is die size, number of metal layers, technology, foundry, number of clocks?
52. * How many macros in your design?
53. * What is each macro size and no. of standard cell count?
54. * How did u handle the Clock in your design?
55. * What are the Input needs for your design?
56. * What is SDC constraint file contains?
57. * How did you do power planning?
58. * How to find total chip power?
59. * How to calculate core ring width, macro ring width and strap or trunk width?
60. * How to find number of power pad and IO power pads?
61. * What are the problems faced related to timing?
62. * How did u resolve the setup and hold problem?
63. * If in your design 10000 and more numbers of problems come, then what you will do?
64. * In which layer do you prefer for clock routing and why?
65. * If in your design has reset pin, then it’ll affect input pin or output pin or both?
66. * During power analysis, if you are facing IR drop problem, then how did u avoid?
67. * Define antenna problem and how did u resolve these problem?
68. * How delays vary with different PVT conditions? Show the graph.
69. * Explain the flow of physical design and inputs and outputs for each step in flow.
70. * What is cell delay and net delay?
71. * What are delay models and what is the difference between them?
72. * What is wire load model?
73. * What does SDC constraints has?
74. * Why higher metal layers are preferred for Vdd and Vss?
75. * What is logic optimization and give some methods of logic optimization.
76. * What is the significance of negative slack?
77. * How the width of metal and number of straps calculated for power and ground?
78. * What is negative slack ? How it affects timing?
79. * What is track assignment?
80. * What is grided and gridless routing?
81. * What is a macro and standard cell?
82. * What is congestion?
83. * Whether congestion is related to placement or routing?
84. * What are clock trees?
85. * What are clock tree types?
86. * Which layer is used for clock routing and why?
87. * What is cloning and buffering?
88. * What are placement blockages?
89. * How slow and fast transition at inputs effect timing for gates?
90. * What is antenna effect?
91. * What are DFM issues?
92. * What is .lib, LEF, DEF, .tf?
93. * What is the difference between synthesis and simulation?
94. * What is metal density, metal slotting rule?
95. * What is OPC, PSM?
96. * Why clock is not synthesized in DC?
97. * What are high-Vt and low-Vt cells?
98. * What corner cells contains?
99. * What is the difference between core filler cells and metal fillers?
100. * How to decide number of pads in chip level design?
101. * What is tie-high and tie-low cells and where it is used * What is signal integrity? How it affects Timing?
102. * What is IR drop? How to avoid .how it affects timing?
103. * What is EM and it effects?
104. * What is floor plan and power plan?
105. * What are types of routing?
106. * What is a grid .why we need and different types of grids?
107. * What is core and how u will decide w/h ratio for core?
108. * What is effective utilization and chip utilization?
109. * What is latency? Give the types?
110. * What is LEF?
111. * What is DEF?
112. * What are the steps involved in designing an optimal pad ring?
113. * What are the steps that you have done in the design flow?
114. * What are the issues in floor plan?
115. * How can you estimate area of block?
116. * How much aspect ratio should be kept (or have you kept) and what is the utilization?
117. * How to calculate core ring and stripe widths?
118. * What if hot spot found in some area of block? How you tackle this?
119. * After adding stripes also if you have hot spot what to do?
120. * What is threshold voltage? How it affect timing?
121. * What is content of lib, lef, sdc?
122. * What is meant my 9 track, 12 track standard cells?
123. * What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
124. * What is setup and hold? Why there are ? What if setup and hold violates?
125. * In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum operating frequency?
126. * How R and C values are affecting time?
127. * How ohm (R), fared (C) is related to second (T)?
128. * What is transition? What if transition time is more?
129. * What is difference between normal buffer and clock buffer?
130. * What is antenna effect? How it is avoided?
131. * What is ESD?
132. * What is cross talk? How can you avoid?
133. * How double spacing will avoid cross talk?
134. * What is difference between HFN synthesis and CTS?
135. * What is hold problem? How can you avoid it?
136. * For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select? Why?
137. * What is partial floor plan?
138. * What parameters (or aspects) differentiate Chip Design & Block level design??
139. * How do you place macros in a full chip design?
140. * Differentiate between a Hierarchical Design and flat design?
141. * Which is more complicated when u have a 48 MHz and 500 MHz clock design?
142. * Name few tools which you used for physical verification?
143. * What are the input files will you give for primetime correlation?
144. * What are the algorithms used while routing? Will it optimize wire length?
145. * How will you decide the Pin location in block level design?
146. * If the routing congestion exists between two macros, then what will you do?
147. * How will you place the macros?
148. * How will you decide the die size?
149. * If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?
150. * If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?
151. * In your project what is die size, number of metal layers, technology, foundry, number of clocks?
152. * How many macros in your design?
153. * What is each macro size and no. of standard cell count?
154. * How did u handle the Clock in your design?
155. * What are the Input needs for your design?
156. * What is SDC constraint file contains?
157. * How did you do power planning?
158. * How to find total chip power?
159. * How to calculate core ring width, macro ring width and strap or trunk width?
160. * How to find number of power pad and IO power pads?
161. * What are the problems faced related to timing?
162. * How did u resolve the setup and hold problem?
163. * If in your design 10000 and more numbers of problems come, then what you will do?
164. * In which layer do you prefer for clock routing and why?
165. * If in your design has reset pin, then it’ll affect input pin or output pin or both?
166. * During power analysis, if you are facing IR drop problem, then how did u avoid?
167. * Define antenna problem and how did u resolve these problem?
168. * How delays vary with different PVT conditions? Show the graph.
169. * Explain the flow of physical design and inputs and outputs for each step in flow.
170. * What is cell delay and net delay?
171. * What are delay models and what is the difference between them?
172. * What is wire load model?
173. * What does SDC constraints has?
174. * Why higher metal layers are preferred for Vdd and Vss?
175. * What is logic optimization and give some methods of logic optimization.
176. * What is the significance of negative slack?
177. * How the width of metal and number of straps calculated for power and ground?
178. * What is negative slack ? How it affects timing?
179. * What is track assignment?
180. * What is grided and gridless routing?
181. * What is a macro and standard cell?
182. * What is congestion?
183. * Whether congestion is related to placement or routing?
184. * What are clock trees?
185. * What are clock tree types?
186. * Which layer is used for clock routing and why?
187. * What is cloning and buffering?
188. * What are placement blockages?
189. * How slow and fast transition at inputs effect timing for gates?
190. * What is antenna effect?
191. * What are DFM issues?
192. * What is .lib, LEF, DEF, .tf?
193. * What is the difference between synthesis and simulation?
194. * What is metal density, metal slotting rule?
195. * What is OPC, PSM?
196. * Why clock is not synthesized in DC?
197. * What are high-Vt and low-Vt cells?
198. * What corner cells contains?
199. * What is the difference between core filler cells and metal fillers?
200. * How to decide number of pads in chip level design?
201. * What is tie-high and tie-low cells and where it is used