1.What is floorplaning?
A. Floor planing is the process of placing Blocks/Macros in the chip/core area, thereby determining the routing areas between them. Floorplan determines the size of die and creates wire tracks for placement of standard cells. It creates power straps and specifies Power Ground(PG) connections. It also determines the I/O pin/pad placement information.
In simple words, Floorplaning is the process of determining the Macro placement, power grid generation and I/O placement.


2. How can you say a floorplan is good?
A. A good floorplaning should meet the following constraints
· Minimize the total chip area
· Make Routing phase easy (Routable)
· Improve the performance by reducing signal delays


3. What are the inputs for floorplan?
A. The following are the inputs for Floorplan
· Synthesized Netlist (.v, .vhdl)\
· Design Constraints (SDC – Synopsys Design Constraints)
· Physical Partitioning Information of the design
· IO Placement file (optional)
· Macro Placement File (optional)

· Floorplaning Control parameters

4. What are the outputs of floorplan?
A. The following are the outputs for floorplan
· Die/Block Area
· I/Os Placed
· Macros placed
· Power Grid Design
· Power Pre-routing
· Standard cell placement areas


5.What are the floorplaning control parameters?
A. Aspect ratio, Core utilization, Row/Core Ratio, Width and eight are the floorplaning control parameters. For more information please visit Floorplaning Control

6. What is the Aspect Ratio?
A. please visit floorplaning control parameters post


7. What is core utilization?
A. please visit floorplaning control parameters post



8. What is total chip utilization?
A. please visit Floorplan control parameters


9. How macro placement is done in floorplaning? or What are the guidelines for macro placement?
A. please visit Macro Placement post


10. What is blockage? What are the different types of blockages? How these blockages are used in physical
design?
A. please visit Blockages and Halos Post


11. What is Halo? How it is useful?
A. Please visit Blockages and Halos Post


12. What are the fly/flight lines? How these fly/flight lines are useful during macroplacement ?
A. Please visit Macro Placement post


13. A netlist consisting of 500k gates and I have to estimate die area and floorplanning. How do I go about it?
A. There are 2 methods to estimate die area

Method 1:
Each cell has got its area according to a specific library. Go through all your cells and multiply each cell in its corresponding area from your vendor's library. Then you can take some density factor - usually for a standard design you should have around 80% density after placement. So from this data you can estimate your
required die area.

Method 2:
One more way of doing it is, Load the design in the implementation tool, try to change the floorplan ( x & y coordinates ) in a such a way that the Starting utilization will be around 50% -to- 60%. Again, it depends on the netlist quality & netlist completion status (like Netlist is 75%, 80% & 90% completed).


14. How to do floor planning for multi Vdd designs?
A. First we have to decide about the power domains, and

add the power rings for each domain, and add the stripes to supply the power for standard cells.


15. How to calculate the power ring width and power straps width and no of power straps using the core power consumption?
A. Please click here for more details


16. What is core utilization percentage?
A. Core utilization percentage indicates the amount of core area  used for cell placement. The number is calculated as a ratio of the total cell area (for hard macros and standard cells or soft macro cells) to the core area. A core utilization of 0.8, for example, means that 80% of the core area is used for cell placement and 20
percent is available for routing.


17.When core utilization area increased to 90%, macros got placed outside core area so does it mean that increase in core utilization area decreases width and height?
A. If you go on with 90% then there may be a problem of congestion and routing problem. It means that you can’t do routing within this area. Sometimes you can fit within 90% utilization but while go on for timing optimization like upsize and adding buffers will lead to increase in size. So in this case you can’t do anything so we need to come back to floorplan again. So to be on safer side we are fixing to 70 to 80% utilization.


18. Why do we remove all placed standard cells, and then write out floorplan in DEF format. What's use of DEF file?
A.DEF deals only with floorplan size. So to get the abstract
of the floorplan, we are doing like this. Saving and loading
this file we can get this abstract again. We don’t need to
redo floorplan.

19. Can area recovery be done by downsizing cells at path with positive slack?
A. Yes, Area recovery can be done by downsizing cells at path with positive slack. Also deleting unwanted buffers will also help in area recovery


20. We can manipulate IR drop by changing number of power straps. I increased power straps which reduced IR drop, but how many power straps can I keep adding to reduce IR drop? How to calculate number of straps required. What problems can arise with
increase in number of straps? 
A. We can use tools to calculate IR drop (ex:- Voltagestrom, Redhawk) if drop is high. Based on that we can add straps. But if you do projects repeatedly you will come to know that this much straps is enough. In this case you will not need tools. It’s having calculation but it’s not accurate it’s an approximate one. Number of straps will create problem in routing also it affects area. So results will be in routing congestion. To number of power straps required for a design click here.


21. aprPGConnect, is used for logical connection of all VDD, VSS nets of all modules. so how do we connect
all VDD, VSS to global VDD /VSS nets before
placement?
A. The aprPGConnect, is used for logical connection of all

VDD, VSS nets of all modules. For physical connection

Timing arcs

What is a timing arc: Static timing analysis works on the concept of timing paths. Each path starts from either primary input or a register and ends at a primary input or register. In-between, the path traverses through what are known as timing arcs. In other words, we can say that timing arc is a component of a timing path. We can define a timing arc as an indivisible path from one pin to another and tells EDA tool to consider the path between the pins. For instance, AND, NAND, NOT, full adder cell etc. gates have arcs from each input pin to each output pin. Also, sequential cells such as flops and latches have arcs from clock pin to output pins and data pins.

Figure 1 : Figure showing cell and net arcs

      Terminology: The common terminology related to timing arcs is as follows:

• Source pin: The pin from which timing arc originates (pin IN1 and IN2 in figure1)
• Sink pin: The pin at which timing arc ends (pin OUT in figure2)

 

Types of arcs: Timing arcs can be categorized into two categories – cell arcs and net arcs.

• ·         Cell arcs: These are between an input pin and output pin of a cell. In other words, source pin is an input pin of a cell and sink pin is an output pin of a cell. In the figure shown above, arcs (IN1 -> OUT) and (IN2 -> OUT) are cell arcs. Cell arcs are further divided into sequential and combinational arcs as discussed below.
   
• ·      Net arcs: These arcs are between driver pin of a net and load pin of a net. In other words, source pin is an output pin of one cell and sink pin is an input pin of another cell. In the figure shown above, arc (OUT -> IN2) is a net arc.

 

Sequential and combinational arcs: As discussed above, cells are can be sequential or combinational. Sequential arcs are between the clock pin of a sequential cell and either input or output pin. Setup and hold arcs are between input data pin and clock pin. Sequential delay arc is between clock pin and output pin of sequential elements. On the other hand, combinational arcs are between an input data and output data pin of a combinational cell or block.

Information contained in timing arc: A timing arc provides following information:

     i)   If the path can be traversed through pin1 to pin2. If the path can be traversed, we say that an arc exists between pin1 and pin2.

     ii)      Under what condition the path will be traversed, known as ‘sdf condition’ 

     iii)     What time it takes from the source pin to the destination pin of the arc to traverse in the path       

      iv)     Timing sense of the arc as explained below

Timing sense: Timing sense of an arc is defined as the sense of traversal from source pin of the timing arc to the sink pin of the timing arc. Timing sense can be ‘positive unate’, ‘negative unate’ and ‘non-unate’.

     ->  Positive unate arc: An arc is said to be positive unite if rise transition at the source pin causes rise transition at sink pin and vice-versa.  Cells of type AND, OR gate etc. have positive unate arcs. All net arcs are positive unate arcs.

     -> Negative unate arc: An arc is said to be negative unite if rise transition at the source pin causes fall transition at the sink pin and vice-versa. NAND, NOR and Inverter have negative unate arcs.

     -> Non unate arcs: If there is no such relationship between the source and sink pins of a timing arc, the arc is said to be non-unate. XOR gate has non-unate timing arcs.

From what source timing arcs are picked: For cell arcs, the existence of arc is picked from liberty files. The cell has a function defined that identifies if the arc is there from its input (say ‘x’) to output (say ‘y’). in most of the cases, the value of the arc is also picked from liberty, but in case you have read SDF, it is picked from SDF (Standard Delay Format) file. On the other hand, for net arcs, the existence of arc is picked from connectivity information (netlist). The net arcs are calculated based on the parasitic values given in SPEF (Standard Parasitics Exchange Format) file, or SDF (like in case above).

Importance of timing arcs: Timing arcs have a very important role in VLSI design industry. Whole of the optimization process right from gate level netlist till final signoff revolves around timing arcs. The presence of correct timing arcs in liberty file is very essential for high quality signoff or there may not be correlation between simulation and silicon).

Library Exchange Format (LEF)

Library Exchange Format (LEF) is a specification for representing the physical layout of an integrate circuit in an ASCII format. It includes design rules and abstract information about the cells. LEF is used in conjunction with Design Exchange Format (DEF) to represent the complete physical layout of an integrated circuit while it is being designed.

An ASCII data format, used to describe a standard cell library Includes the design rules for routing and the Abstract of the cells, no information about the internal netlist of the cells

A LEF file contains the following sections:

�� Technology: layer, design rules, via definitions, metal capacitance

�� Site: Site extension

�� Macros: cell descriptions, cell dimensions, layout of pins and blockages, capacitances.

The technology is described by the Layer and Via statements. To each layer the following  attributes may be associated:

�� type: Layer type can be routing, cut (contact), masterslice (poly, active),overlap.

�� width/pitch/spacing rules

�� direction

�� resistance and capacitance per unit square

�� antenna Factor

Layers are defined in process order from bottom to top

poly masterslice

cc cut

metal1 routing

via cut

metal2 routing

via2 cut

metal3 routing

Cut Layer definition

LAYER

 layername

TYPE CUT

;

SPACING

Specifies the minimum spacing allowed between via cuts on the same net or different nets. This value can be overridden by the SAMENET SPACING statement (we are going to use this statement later)END layerName 

Implant Layer definition

LAYER layerName

TYPE IMPLANT ;

SPACING minSpacing

END layerName

Defines implant layers in the design. Each layer is defined by assigning it a name and simple spacing and width rules. These spacing and width rules only affect the legal cell placements. These rules interact with the library methodology, detailed placement, and filler cell support.

Masterslice or Overlap Layer definition

LAYER layerName

TYPE {MASTERSLICE | OVERLAP} ;

Defines masterslice (nonrouting) or overlap layers in the design. Masterslice layers are typically polysilicon layers and are only needed if the cell MACROs have pins on the polysilicon layer.

Routing Layer definition

LAYER layerName

TYPE ROUTING ;

DIRECTION {HORIZONTAL | VERTICAL} ;

PITCH distance;

WIDTH defWidth;

OFFSET distance ;

SPACING minSpacing;

RESISTANCE RPERSQ value ;

Specifies the resistance for a square of wire, in ohms per square.  The resistance of a wire can be defined as RPERSQU x wire length/wire width

CAPACITANCE CPERSQDIST value ;

Specifies the capacitance for each square unit, in picofarads per square micron. This is used to model wire-to-ground capacitance.

Manufacturing Grid

MANUFACTURINGGRID value ;

Defines the manufacturing grid for the design. The manufacturing grid is used for geometry alignment. When specified, shapes and cells are placed in locations that snap to the manufacturing grid.

Via

VIA viaName

DEFAULT

TOPOFSTACKONLY

FOREIGN foreignCellName [pt [orient]] ;

RESISTANCE value ;

{LAYER layerName ;

{RECT pt pt ;} ...} ...

END viaName

Defines vias for usage by signal routers. Default vias have exactly three layers used:

 A cut layer, and two layers that touch the cut layer (routing or masterslice). The cut layer rectangle must be between the two routing or masterslice layer rectangles.

Via Rule Generate

VIARULE viaRuleName GENERATE

LAYER routingLayerName ;

{ DIRECTION {HORIZONTAL | VERTICAL} ;

OVERHANG overhang ;

METALOVERHANG metalOverhang ;

| ENCLOSURE overhang1 overhang2 ;}

LAYER routingLayerName ;

{ DIRECTION {HORIZONTAL | VERTICAL} ;

OVERHANG overhang ;

METALOVERHANG metalOverhang ;

| ENCLOSURE overhang1 overhang2 ;}

LAYER cutLayerName ;

RECT pt pt ;

SPACING xSpacing BY ySpacing ;

RESISTANCE resistancePerCut ;

END viaRuleName

Defines formulas for generating via arrays. Use the VIARULE GENERATE statement to cover special wiring that is not explicitly defined in the VIARULE statement.

Same-Net Spacing

SPACING

SAMENET layerName layerName minSpace [STACK] ; ...

END SPACING

Defines the same-net spacing rules. Same-net spacing rules determine minimum spacing between geometries in the same net and are only required if same-net spacing is smaller than different-net spacing, or if vias on different layers have special stacking rules.

Thesespecifications are used for design rule checking by the routing and verification tools.

Spacing is the edge-to-edge separation, both orthogonal and diagonal.

Site

SITE siteName

CLASS {PAD | CORE} ;

[SYMMETRY {X | Y | R90} ... ;] (will discuss this later in macro definition)

SIZE width BY height ;

END siteName

Macro

MACRO macroName

[CLASS

{ COVER [BUMP]

| RING

| BLOCK [BLACKBOX]

| PAD [INPUT | OUTPUT |INOUT | POWER | SPACER | AREAIO]

| CORE [FEEDTHRU | TIEHIGH | TIELOW | SPACER | ANTENNACELL]

| ENDCAP {PRE | POST | TOPLEFT | TOPRIGHT | BOTTOMLEFT | BOTTOMRIGHT}

}

;]

[SOURCE {USER | BLOCK} ;]

[FOREIGN foreignCellName [pt [orient]] ;] ...

[ORIGIN pt ;]

[SIZE width BY height ;]

[SYMMETRY {X | Y | R90} ... ;]

[SITE siteName ;]

[PIN statement] ...

[OBS statement] ...

Macro Pin Statement

PIN pinName

FOREIGN foreignPinName [STRUCTURE [pt [orient] ] ] ;

[DIRECTION {INPUT | OUTPUT [TRISTATE] | INOUT | FEEDTHRU} ;]

[USE { SIGNAL | ANALOG | POWER | GROUND | CLOCK } ;]

[SHAPE {ABUTMENT | RING | FEEDTHRU} ;]

[MUSTJOIN pinName ;]

{PORT

[CLASS {NONE | CORE} ;]

{layerGeometries} ...

END} ...

END pinName]

Macro Obstruction Statement

OBS

{ LAYER layerName [SPACING minSpacing | DESIGNRULEWIDTH value] ;

RECT pt pt ;

POLYGON pt pt pt pt ... ;

END

Difference Between CCS and NLDM

What is CCS and NLDM:

CCS stands for Composit Current Sourse Model, and NLDM stands for Non-Linear Delay Model. Both CCS & NLDM are delay models used in timing analyze.

Difference between CCS & NLDM:

• NLDM uses a voltage source for driver modeling
• CCS uses a current source for driver modeling

Why prefer CCS to NLDM:

The issues with NLDM modeling is that, when the drive resistance RD becomes much less than Znet(network load impedance), then ideal condition arises i.e Vout=Vin. Which is impossible in practical conditions.

So with NLDM modeling parameters like the cell delay calculation, skew calculation will be inaccurate.

That is the reason why we prefer CCS to NLDM

DIFFERENT TYPES OF FILE FORMATS AND THEIR MEANINGS IN VLSI.

There are different type of the files generated during a design cycle or data received by the library vendor/foundry. Few of them having specific extension. Just to know the extension, you can easily identity the type of content in that file.

 *.ddc - Synopsys internal database format. This format is recommended by Synopsys to hand gate-level netlists.File Extensions: 

*.v - Verilog source file. Normally it’s a source file your write. Design Compiler, and IC Compiler can use this format for the gate-level netlist.

*.vg, .g.v - Verilog gate-level netlist file. Sometimes people use these file extension to differentiate source files and gate-level netlists.

*.svf - Automated setup file. This file helps Formality process design changes caused by other tools used in the design flow. Formality uses this file to assist the compare point matching and verification process. This information facilitates alignment of compare points in the designs that you are verifying. For each automated setup file that you load, Formality processes the content and stores the information for use during the name-based compare point matching period.

 *.vcd - Value Change Dump format. This format is used to save signal transition trace information. This format is in text format, therefore, the trace file in this format can get very large quickly. There are tools like vcd2vpd, vpd2vcd, and vcd2saif switch back and forth between different formats.

*.vpd - VCD Plus. This is a proprietary compressed binary trace format from Synopsys. This file format is used to save signal transition trace information as well.

 *.saif - Switching Activity Interchange Format. It’s another format to save signal transition trace information. SAIF files support signals and ports for monitoring as well as constructs such as generates, enumerated types, records, array of arrays, and integers.

 *.tcl - Tool Command Language (Tcl) scripts. Tcl is used to drive Synopsys tools.

 *.sdc - Synopsys Design Constraints. SDC is a Tcl-based format. All commands in an SDC file conform to the Tcl syntax rules. You use an SDC file to communicate the design intent, including timing and area requirements between EDA tools. An SDC file contains the following information: SDC version, SDC units, design constraints, and comments. 

 *.lib - Technology Library source file. Technology libraries contain information about the characteristics and functions of each cell provided in a semiconductor vendor’s library. Semiconductor vendors maintain and distribute the technology libraries. In our case the vendor is Synopsys. Cell characteristics include information such as cell names, pin names, area, delay arcs, and pin loading. The technology library also defines the conditions that must be met for a functional design (for example, the maximum transition time for nets). These conditions are called design rule constraints. In addition to cell information and design rule constraints, technology libraries specify the operating conditions and wire load models specific to that technology.

 *.db - Technology Library. This is a compiled version of *.lib in Synopsys database format.

 *.plib - Physical Library source file. Physical libraries contain process information, and physical layout information of the cells. This information is required for floor planning, RC estimation and extraction, placement, and routing.

 *.pdb - Physical Library. This is a compiled version of *.plib in Synopsys database format.

 *.slib - Symbol Library source file. Symbol libraries contain definitions of the graphic symbols that represent library cells in the design schematics. Semiconductor vendors maintain and distribute the symbol libraries. Design Compiler uses symbol libraries to generate the design schematic. You must use Design Vision to view the design schematic. When you generate the design schematic, Design Compiler performs a one-to-one mapping of cells in the netlist to cells in the symbol library.

 *.sdb - Symbol Library. This is a compiled version of *.slib in Synopsys database format.

 *.sldb - DesignWare Library. This file contains information about DesignWare libraries.

 *.def - Design Exchange Format. This format is often used in Cadence tools to represent physical layout. Synopsys tools normally use Milkyway format to save designs.

 *.lef - Library Exchange Format. Standard cells are often saved in this format. Cadence tools also often use this format. Synopsys tools normally use Milkyway format for standard cells.

 *.rpt - Reports. This is not a proprietary format, it’s just a text format which saves generated reports by the tools when you use the automated makefiles and scripts.

 *.tf - Vendor Technology File. This file contains technology-specific information such as the names, characteristics (physical and electrical) for each metal layer, and design rules. These information are required to route a design.

 *.itf - Interconnect Technology File. This file contains a description of the process crosssection and connectivity section. It also describes the thicknesses and physical attributes of the conductor and dielectric layers.

 *.map - Mapping file. This file aligns names in the vendor technology file with the names in the process *.itf file.

 *.tluplus - TLU+ file. These files are generated from the *.itf files. TLUPlus models are a set of models containing advanced process effects that can be used by the parasitic extractors in Synopsys place-and-route tools for modeling.

 *.spef - Standard Parasitic Exchange Format. File format to save parasitic information extracted by the place and route tool.

 *.sbpf - Synopsys Binary Parasitic Format. A Synopsys proprietary compressed binary format of the *.spef. Size of the file shrinks quite a bit using this format.

*.mw( Milkyway database) The Milkyway database consists of libraries that contain information about your design. Libraries contain information about design cells, standard cells, macro cells, and so on. They contain physical descriptions, such as metal, diffusion, and polygon geometries. Libraries also contain logical information (functionality and timing characteristics) for every cell in the library. Finally, libraries contain technology information required for design and fabrication. Milkyway provides two types of libraries that you can use: reference libraries and design libraries. Reference libraries contain standard cells and hard or soft macro cells, which are typically created by vendors. Reference libraries contain physical information necessary for design implementation. Physical information includes the routing directions and the placement unit tile dimensions, which is the width and height of the smallest instance that can be placed. A design library contains a design cell. The design cell might contain references to multiple reference libraries (standard cells and macro cells). Also, a design library can be a reference library for another design library. The Milkyway library is stored as a UNIX directory with subdirectories, and every library is managed by the Milkyway Environment. The top-level directory name corresponds to the name of the Milkyway library. Library subdirectories are classified into different views containing the appropriate information relevant to the library cells or the designs. In a Milkyway library there are different views for each cell, for example, NOR1.CEL and NOR1.FRAM. This is unlike a .db formatted library where all the cells are in a single binary file. With a .db library, the entire library has to be read into memory. In the Milkyway Environment, the Synopsys tool loads the library data relevant to the design as needed, reducing memory usage. The most commonly used Milkyway views are CEL and FRAM. CEL is the full layout view, and FRAM is the abstract view for place and route operations.

 simv - Compiled simulator. This is the output of vcs. In order to simulate, run the simulator by ./simv at the command line.

 alib-52 - characterized target technology library. A pseudo library which has mappings from Boolean functional circuits to actual gates from the target library. This library provides Design Compiler with greater flexibility and a larger solution space to explore tradeoffs between area and delay during optimization.

Inputs to Physical Design

·         In Physical Design mainly Six inputs are present

1.    Logical libraries      --> format is .lib    --->given by Vendors

2.    physical libraries    -->format is .lef     --->given by vendors

3.    Technology file       -->format is .tf       --->given by fabrication peoples

4.    TLU+ file                   -->format is .TLUP-->given by fabrication people

5.    Netlist                      --->format is .v       -->given by Synthesis People

6.    Synthesis Design Constraints  -->format is .SDC   -->given by Synthesis People

LOGICAL LIBRARIES

Logical libraries :format is .lib

1.    Timing information of Standard cells,Soft macros,Hard macros.

2.    functionality  information of Standard cells,Soft macros.

3.    And design rules like max transition ,max capacitance, max fanout.

4.    In timing information Cell delays ,Setup,Hold time are present.

5.    Cell delay is Function of input transition and output load.

6.    Cell delay is calculated based on lookup tables.

7.    Cell delays are calculated by using linear delay models,Non linear delay models,CCS models.

8.    functionality  is used for Optimization Purpose.

9.    And also Contain Power information.

10.  And contains Leakage power for Default cell,Leakage Power Density for cell,Default Input voltage , Out put voltage.

And PVT contains ------->Cell leakage Power
                             -------->Internal Power
                            --------->Rise Transition
                              
And it contains A view(sub directory) i.e. LM(Logical Model view)view.
It contains logical libraries.

PHYSICAL LIBRARIES

Physical libraries: format is .lef:

1.    physical information of std cells,macros,pads.

2.    Pin information.

3.    Define unit tile placement.

4.    Minimum Width of Resolution.

5.    Hight of the placement Rows .

6.    Preferred routing Directions.

7.    Pitch of the routing tracks.

8.    Antena Rules.

9.    Routing Blockages

In physical info height,area,width are present.
and also it contains two views
1)Cell View:
In this all layout information is present,it is used at the time of tapeout
2)FRAM view:
Fram view is abstract view, it is used at the Place & Route

TECHNOLOGY FILE

Technology file: format is .tf:

1.    It contains Name,Number conventions of layer and via

2.    It contains Physical,electrical characteristics of  layer and via

3.    In Physical characteristics Min width,area,height are present.

4.    In Electrical characteristics Current Density is present.

5.    Units and Precisions of layer and via .

6.    Colors and pattern of layer and via .

7.    Physical Design rules of layer and via

8.    In Physical Design rules Wire to Wire Spacing,Min Width between Layer and via are present.

TLU PLUS 

TLU+ files: format is .TLUP:

1.    R,C parasitics of metal per unit length.

2.    These(R,C parasitics) are used for calculating Net Delays.

3.    If TLU+ files are not given then these are getting from .ITF file.

4.    For Loading TLU+ files we have load three files .

5.    Those are Max Tlu+,Min TLU+,MAP file.

6.    MAP file maps the .ITF file and .tf file of the layer and via names.

NETLIST

Netlist: Format is .V

It contains Logical connectivity Of all Cell(Std cells,Macros).
It contain List of nets.
In the design for Knowing connectivity by using Fly lines.

SDC

SDC :Format is .SDC :

These Constraints are timing Constraints .
These Constraints used for to meet timing requirements.
Constraints are

1.    CLOCK DEFINITIONS:Create Clock Period.

2.    Generated Clock Definitions

3.    Input Delay

4.    Output Delay

5.    I/O delay

6.    Max delay

7.    Min Delay

8.    --------------->Exceptions<-------------------------

9.    Multi cycle path

10.  False path

11.  Half cycle path

12.  Disable timing arcs

13.  Case Analysis

Multi cycle path, False path are Exceptions.