1.List the advantages of SOI CMOS process
• Denser transistor structures are possible.
• Lower substrate capacitances
• No field inversion problem
• No latch up
• No body effect problem
• Enhanced radiation tolerance
2. Distinguish electrically alterable & non-electrically alterable ROM
In electrically alterable ROM the cell can be turned ON or OFF by controlling the voltages applied to the control gate, source and drain voltages. In non-electrically alterable ROM versions, the process can only be reversed by illuminating the gate with UV light.
3. How do you prevent latch up problem?
Latch up problem can be reduced by reducing the gain of parasitic transistors and resistors. It can be prevented in 2 ways
• Latch up resistant CMOS program
• Layout technique
The various lay out techniques are
Internal latch up prevention technique
I/O latch up prevention technique.
4.List the basic process for IC fabrication
_ Silicon wafer Preparation
_ Epitaxial Growth
_ Oxidation
_ Photolithography
_ Diffusion
_ Ion Implantation
_ Isolation technique
_ Metallization
_ Assembly processing & Packaging
5. What are the various Silicon wafer Preparation?
_ Crystal growth & doping
_ Ingot trimming & grinding
_ Ingot slicing
_ Wafer polishing & etching
_ Wafer cleaning.
6.Different types of oxidation?
Dry & Wet Oxidation
7.What are the advantages of CMOS process?
Low power Dissipation
High Packing density
Bi directional capability
Low Input Impedance
Low delay Sensitivity to load.
8.What is pull down device?
A device connected so as to pull the output voltage to the lower supply voltage usually 0V is called pull down device.
9.What is pull up device?
A device connected so as to pull the output voltage to the upper supply voltage usually
VDD is called pull up device.
10.. Why NMOS technology is preferred more than PMOS technology?
N- channel transistors has greater switching speed when compared tp PMOS transistors.
11. What are the different operating regions foe an MOS transistor?
_ Cutoff region
_ Non- Saturated Region
_ Saturated Region
12.What is Channel-length modulation?
The current between drain and source terminals is constant and independent of the applied voltage over the terminals. This is not entirely correct. The effective length of the conductive channel is actually modulated by the applied VDS, increasing VDS causes the depletion region at the drain junction to grow, reducing the length of the effective channel.
13. What is Latch – up?
Latch up is a condition in which the parasitic components give rise to the establishment of low resistance conducting paths between VDD and VSS with disastrous results. Careful control during fabrication is necessary to avoid this problem.
14.What is Stick Diagram?
It is used to convey information through the use of color code. Also it is the cartoon of a chip layout.
15.What are the uses of Stick diagram?
_ It can be drawn much easier and faster than a complex layout.
_ These are especially important tools for layout built from large cells.
16.Give the various color coding used in stick diagram?
_ Green – n-diffusion
_ Red- polysilicon
_ Blue –metal
_ Yellow- implant
_ Black-contact areas.
17.Define Threshold voltage in CMOS?
The Threshold voltage, VT for a MOS transistor can be defined as the voltage applied between the gate and the source of the MOS transistor below which the drain to source current, IDS effectively drops to zero.
18.What is Body effect?
The threshold volatge VT is not a constant w. r. to the voltage difference between the substrate and the source of MOS transistor. This effect is called substrate-bias effect or body effect.
19.What is LOCOS?
LOCOS mean Local Oxidation of Silicon. This is one type of oxide construction.
20. Compare between CMOS and bipolar technologies.
21.What are the various cmos technologies?
Various cmos technologies are,
I) n- well process or n -tub process
ii) p well process or p-tub process
iii) Twin tub process
iv) Silicon on Insulator (SOI) process
22.What is channel-stop implantation?
In n -well fabrication, n-well is protected with resist material. Because it should not be affected by boron implantation. Then boron is implanted except n-well. It is done using photo resist mask. This type of implantation is known as channel-stop implantation.
23.What is SWAMI?
SWAMI means Side Wall Masked Isolation. It is used to reduce bird’s beak effect.
24.What is LDD?
LDD means Lightly Doped Drain structures. It is used for implantation of n-in n-well process. T
25.What is twin tub process? Why it is so called?
Twin tub process is one of cmos technology. There are two wells available in this process. The other name of well is tub. so because of these two tubs, this process is known as twin tub process.
26.What are the special features of twin tub process?
In twin tub process, threshold voltages, body effect of n and p devices are independently optimized.
27.What are the advantages of twin tub process?
Advantages of twin tub process are
1) Separate optimized wells are available.
2) Balanced performance is obtained for n and p transistors.
28.What is SOI? What is the material used as insulator?
SOI means Silicon –On-Insulator. In this process, sapphire or sio2 is used as insulator.
29.What are the various etching processes used in SOI process?
Various etching process used in SOI are,
1) Isotropic etching process
2) Anisotropic etching process
3) Preferential etching process
30.What are the advantages and disadvantages of SOI process?
Advantages of SOI process
There is no well formation in this process
There is no field –Inversion problem.
There is no body effect problem.
Disadvantages of SOI process
It is very difficult to protect inputs in this process.
Device gain is low.
The coupling capacitance between wires always exists.
31.What is silicide?
The combination of Silicon and tantalum is known as Silicide. It is used as gate materials in polysilicon interconnect.
32. Compare nMOS and pMOS devices
nMOS pMOS
A section of p-type separating 2 n-type silicon A section of n-type separating 2 p type silicon
Turns ON with the gate at logic 1 Turns ON with the gate at logic 0
Majority carriers are electrons Majority carriers are holes
Good transmission of logic 0 Good transmission of logic 1
33. Compare enhancement and depletion mode devices
In n-type enhancement MOS a narrow region of p-type substrate is covered by a layer of SiO2. In n-type depletion substrate a lightly doped n-region is diffused between the two heavily doped source and drain.
34. Which MOS can pass logic1 and logic 0 stongly?
p-mos can pass strong logic 1
n-mos can pass strong logic 0.
35. What is meant by a transmission gate?
A transmission gate consists of an n-channel transistor and p-channel transistor with separate gates and common source and drain. Its symbol is
36.Define Rise time
Rise time, tr is the time taken for a waveform to rise from 10% to 90% of its steady-state value.
37. Define Fall time
Fall time, f is the time taken for a waveform to fall from 90% to 10% of its steady-state value.
38. Define Delay time
Delay time, d is the time difference between input transition (50%) and the 50% output
level. This is the time taken for a logic transition to pass from input to output
39.Define noise margin.
The parameter which gives the quantitative measure of how stable the inputs are with respect to coupled electromagnetic signal interference.
NML = Vil-Vol
NMH = Voh-Vih
40.Define rise time and fall time
Rise time is defined as the time for a waveform to rise from 10% to 90% of its steady-state value.
Fall time is defined as the time for a waveform to fall from 90% to 10% of its steady state value.
41. What is meant by continuous assignment statement in verilog HDL?
A continuous assignment assigns a value to a net. The syntax is assign_LHS target = RHS _ expression;
Ex: assign Z = (A I B) ;
42. What is a task in verilog?
A task is like a procedure, it provides the ability to execute common pieces of code from several different places in a description
43.Mention few data types in Verilog
Nets, registers, vectors, numbers and arrays
44.Mention the four key words used for looping in verilog
while, for, repeat, forever
45.Give the basic difference between tasks and functions.
Functions always return a single value. They cannot have output or in-out arguments. Tasks don’t return a value, but can pass multiple values through output and inout arguments.
46.Specify the operator which have highest and lowest precedence.
Unary operator – highest precedence
Conditional operator – lowest precedence
47.what are bit wise operators in verilog?
Bit wise operators are,
׀ – binary or
~ – Unary negation
^ – Exclusive –or
~ ^ – Exclusive –nor
& – and
48.Give the examples for procedural statement.
Loop statement , Wait statement
Conditional statement, Case statement
49.In behavioral modeling specify the two most basic statements.
Initial and always statements
50.Blocking and non-blocking statements differ in executing the statements . How?
Blocking statements are executed in the order in which they are specified in a sequential block. “= “is the operator used to specify blocking assignments.
Non blocking statements allow scheduling of assignments without blocking execution of the statement that follow in a sequential block. “<=” is the operator used to specify non blocking assignment.
51.Specify the three method of timing control.
Delay based timing control
Event based timing control
Level sensitive timing control
52. What are the various modeling used in Verilog?
1. Gate-level modeling
2. Data-flow modeling
3. Switch-level modeling
4. Behavioral modeling
53. What is the structural gate-level modeling?
Structural modeling describes a digital logic networks in terms of the components that make up the system. Gate-level modeling is based on using primitive logic gates and specifying how they are wired together.
54.What is Switch-level modeling?
Verilog allows switch-level modeling that is based on the behavior of MOSFETs.Digital circuits at the MOS-transistor level are described using the MOSFET switches.
55. What are identifiers?
Identifiers are names of modules, variables and other objects that we can
reference in the design. Identifiers consists of upper and lower case letters, digits
0 through 9, the underscore character(_) and the dollar sign($). It must be a single
group of characters.
Examples: A014, a ,b, in_o, s_out
56. What are the value sets in Verilog?
Verilog supports four levels for the values needed to describe hardware referred to as value sets.
57.Value levels Condition in hardware circuits
0 Logic zero, false condition
1 Logic one, true condition
X Unknown logic value
Z High impedance, floating state
58. Give the classifications of timing control?
Methods of timing control:
1. Delay-based timing control
2. Event-based timing control
3. Level-sensitive timing control
Types of delay-based timing control:
1. Regular delay control
2. Intra-assignment delay control
3. Zero delay control
Types of event-based timing control:
1. Regular event control
2. Named event control
3. Event OR control
4. Level-sensitive timing control
59. Give the different arithmetic operators?
Operator symbol Operation performed Number of operands
* Multiply Two
/ Divide Two
+ Add Two
– Subtract Two
% Modulus Two
** Power (exponent) Two
60.. Give the different bitwise operators.
Operator symbol Operation performed Number of operands
~ Bitwise negation One
& Bitwise and Two
| Bitwise or Two
^ Bitwise xor Two
^~ or ~^ Bitwise xnor Two
~& Bitwise nand Two
~| Bitwise nor Two
61. What are gate primitives?
Verilog supports basic logic gates as predefined primitives. Primitive logic
function keyword provide the basics for structural modeling at gate level. These
primitives are instantiated like modules except that they are predefined in verilog
and do not need a module definition. The important operations are and, nand, or,
xor, xnor, and buf(non-inverting drive buffer).
62. Give the two blocks in behavioral modeling.
1. An initial block executes once in the simulation and is used to set up
initial conditions and step-by-step data flow
2. An always block executes in a loop and repeats during the simulation.
63. What are the types of conditional statements?
1. No else statement
Syntax : if ( [expression] ) true – statement;
2. One else statement
Syntax : if ( [expression] ) true – statement;
else false-statement;
3. Nested if-else-if
Syntax : if ( [expression1] ) true statement 1;
else if ( [expression2] ) true-statement 2;
else if ( [expression3] ) true-statement 3;
else default-statement;
The [expression] is evaluated. If it is true (1 or a non-zero value) true-statement is
executed. If it is false (zero) or ambiguous (x), the false-statement is executed.
64. Name the types of ports in Verilog
Types of port Keyword
Input port Input
Output port Output
Bidirectional port inout
65. What are the types of procedural assignments?
1. Blocking assignment
2. Non-blocking assignment
• Denser transistor structures are possible.
• Lower substrate capacitances
• No field inversion problem
• No latch up
• No body effect problem
• Enhanced radiation tolerance
2. Distinguish electrically alterable & non-electrically alterable ROM
In electrically alterable ROM the cell can be turned ON or OFF by controlling the voltages applied to the control gate, source and drain voltages. In non-electrically alterable ROM versions, the process can only be reversed by illuminating the gate with UV light.
3. How do you prevent latch up problem?
Latch up problem can be reduced by reducing the gain of parasitic transistors and resistors. It can be prevented in 2 ways
• Latch up resistant CMOS program
• Layout technique
The various lay out techniques are
Internal latch up prevention technique
I/O latch up prevention technique.
4.List the basic process for IC fabrication
_ Silicon wafer Preparation
_ Epitaxial Growth
_ Oxidation
_ Photolithography
_ Diffusion
_ Ion Implantation
_ Isolation technique
_ Metallization
_ Assembly processing & Packaging
5. What are the various Silicon wafer Preparation?
_ Crystal growth & doping
_ Ingot trimming & grinding
_ Ingot slicing
_ Wafer polishing & etching
_ Wafer cleaning.
6.Different types of oxidation?
Dry & Wet Oxidation
7.What are the advantages of CMOS process?
Low power Dissipation
High Packing density
Bi directional capability
Low Input Impedance
Low delay Sensitivity to load.
8.What is pull down device?
A device connected so as to pull the output voltage to the lower supply voltage usually 0V is called pull down device.
A device connected so as to pull the output voltage to the upper supply voltage usually
VDD is called pull up device.
10.. Why NMOS technology is preferred more than PMOS technology?
N- channel transistors has greater switching speed when compared tp PMOS transistors.
11. What are the different operating regions foe an MOS transistor?
_ Cutoff region
_ Non- Saturated Region
_ Saturated Region
12.What is Channel-length modulation?
The current between drain and source terminals is constant and independent of the applied voltage over the terminals. This is not entirely correct. The effective length of the conductive channel is actually modulated by the applied VDS, increasing VDS causes the depletion region at the drain junction to grow, reducing the length of the effective channel.
13. What is Latch – up?
Latch up is a condition in which the parasitic components give rise to the establishment of low resistance conducting paths between VDD and VSS with disastrous results. Careful control during fabrication is necessary to avoid this problem.
14.What is Stick Diagram?
It is used to convey information through the use of color code. Also it is the cartoon of a chip layout.
15.What are the uses of Stick diagram?
_ It can be drawn much easier and faster than a complex layout.
_ These are especially important tools for layout built from large cells.
16.Give the various color coding used in stick diagram?
_ Green – n-diffusion
_ Red- polysilicon
_ Blue –metal
_ Yellow- implant
_ Black-contact areas.
17.Define Threshold voltage in CMOS?
The Threshold voltage, VT for a MOS transistor can be defined as the voltage applied between the gate and the source of the MOS transistor below which the drain to source current, IDS effectively drops to zero.
18.What is Body effect?
The threshold volatge VT is not a constant w. r. to the voltage difference between the substrate and the source of MOS transistor. This effect is called substrate-bias effect or body effect.
19.What is LOCOS?
LOCOS mean Local Oxidation of Silicon. This is one type of oxide construction.
20. Compare between CMOS and bipolar technologies.
21.What are the various cmos technologies?
Various cmos technologies are,
I) n- well process or n -tub process
ii) p well process or p-tub process
iii) Twin tub process
iv) Silicon on Insulator (SOI) process
22.What is channel-stop implantation?
In n -well fabrication, n-well is protected with resist material. Because it should not be affected by boron implantation. Then boron is implanted except n-well. It is done using photo resist mask. This type of implantation is known as channel-stop implantation.
23.What is SWAMI?
SWAMI means Side Wall Masked Isolation. It is used to reduce bird’s beak effect.
24.What is LDD?
LDD means Lightly Doped Drain structures. It is used for implantation of n-in n-well process. T
25.What is twin tub process? Why it is so called?
Twin tub process is one of cmos technology. There are two wells available in this process. The other name of well is tub. so because of these two tubs, this process is known as twin tub process.
26.What are the special features of twin tub process?
In twin tub process, threshold voltages, body effect of n and p devices are independently optimized.
27.What are the advantages of twin tub process?
Advantages of twin tub process are
1) Separate optimized wells are available.
2) Balanced performance is obtained for n and p transistors.
28.What is SOI? What is the material used as insulator?
SOI means Silicon –On-Insulator. In this process, sapphire or sio2 is used as insulator.
29.What are the various etching processes used in SOI process?
Various etching process used in SOI are,
1) Isotropic etching process
2) Anisotropic etching process
3) Preferential etching process
30.What are the advantages and disadvantages of SOI process?
Advantages of SOI process
There is no well formation in this process
There is no field –Inversion problem.
There is no body effect problem.
Disadvantages of SOI process
It is very difficult to protect inputs in this process.
Device gain is low.
The coupling capacitance between wires always exists.
31.What is silicide?
The combination of Silicon and tantalum is known as Silicide. It is used as gate materials in polysilicon interconnect.
32. Compare nMOS and pMOS devices
nMOS pMOS
A section of p-type separating 2 n-type silicon A section of n-type separating 2 p type silicon
Turns ON with the gate at logic 1 Turns ON with the gate at logic 0
Majority carriers are electrons Majority carriers are holes
Good transmission of logic 0 Good transmission of logic 1
33. Compare enhancement and depletion mode devices
In n-type enhancement MOS a narrow region of p-type substrate is covered by a layer of SiO2. In n-type depletion substrate a lightly doped n-region is diffused between the two heavily doped source and drain.
34. Which MOS can pass logic1 and logic 0 stongly?
p-mos can pass strong logic 1
n-mos can pass strong logic 0.
35. What is meant by a transmission gate?
A transmission gate consists of an n-channel transistor and p-channel transistor with separate gates and common source and drain. Its symbol is
Rise time, tr is the time taken for a waveform to rise from 10% to 90% of its steady-state value.
37. Define Fall time
Fall time, f is the time taken for a waveform to fall from 90% to 10% of its steady-state value.
38. Define Delay time
Delay time, d is the time difference between input transition (50%) and the 50% output
level. This is the time taken for a logic transition to pass from input to output
39.Define noise margin.
The parameter which gives the quantitative measure of how stable the inputs are with respect to coupled electromagnetic signal interference.
NML = Vil-Vol
NMH = Voh-Vih
40.Define rise time and fall time
Rise time is defined as the time for a waveform to rise from 10% to 90% of its steady-state value.
Fall time is defined as the time for a waveform to fall from 90% to 10% of its steady state value.
A continuous assignment assigns a value to a net. The syntax is assign_LHS target = RHS _ expression;
Ex: assign Z = (A I B) ;
A task is like a procedure, it provides the ability to execute common pieces of code from several different places in a description
Nets, registers, vectors, numbers and arrays
while, for, repeat, forever
Functions always return a single value. They cannot have output or in-out arguments. Tasks don’t return a value, but can pass multiple values through output and inout arguments.
Conditional operator – lowest precedence
Bit wise operators are,
׀ – binary or
~ – Unary negation
^ – Exclusive –or
~ ^ – Exclusive –nor
& – and
Loop statement , Wait statement
Conditional statement, Case statement
Initial and always statements
Blocking statements are executed in the order in which they are specified in a sequential block. “= “is the operator used to specify blocking assignments.
Non blocking statements allow scheduling of assignments without blocking execution of the statement that follow in a sequential block. “<=” is the operator used to specify non blocking assignment.
Delay based timing control
Event based timing control
Level sensitive timing control
1. Gate-level modeling
2. Data-flow modeling
3. Switch-level modeling
4. Behavioral modeling
Structural modeling describes a digital logic networks in terms of the components that make up the system. Gate-level modeling is based on using primitive logic gates and specifying how they are wired together.
Verilog allows switch-level modeling that is based on the behavior of MOSFETs.Digital circuits at the MOS-transistor level are described using the MOSFET switches.
reference in the design. Identifiers consists of upper and lower case letters, digits
0 through 9, the underscore character(_) and the dollar sign($). It must be a single
group of characters.
Examples: A014, a ,b, in_o, s_out
Verilog supports four levels for the values needed to describe hardware referred to as value sets.
0 Logic zero, false condition
1 Logic one, true condition
X Unknown logic value
Z High impedance, floating state
Methods of timing control:
1. Delay-based timing control
2. Event-based timing control
3. Level-sensitive timing control
Types of delay-based timing control:
1. Regular delay control
2. Intra-assignment delay control
3. Zero delay control
Types of event-based timing control:
1. Regular event control
2. Named event control
3. Event OR control
4. Level-sensitive timing control
Operator symbol Operation performed Number of operands
* Multiply Two
/ Divide Two
+ Add Two
– Subtract Two
% Modulus Two
** Power (exponent) Two
Operator symbol Operation performed Number of operands
~ Bitwise negation One
& Bitwise and Two
| Bitwise or Two
^ Bitwise xor Two
^~ or ~^ Bitwise xnor Two
~& Bitwise nand Two
~| Bitwise nor Two
function keyword provide the basics for structural modeling at gate level. These
primitives are instantiated like modules except that they are predefined in verilog
and do not need a module definition. The important operations are and, nand, or,
xor, xnor, and buf(non-inverting drive buffer).
1. An initial block executes once in the simulation and is used to set up
initial conditions and step-by-step data flow
2. An always block executes in a loop and repeats during the simulation.
1. No else statement
Syntax : if ( [expression] ) true – statement;
2. One else statement
Syntax : if ( [expression] ) true – statement;
else false-statement;
3. Nested if-else-if
Syntax : if ( [expression1] ) true statement 1;
else if ( [expression2] ) true-statement 2;
else if ( [expression3] ) true-statement 3;
else default-statement;
The [expression] is evaluated. If it is true (1 or a non-zero value) true-statement is
executed. If it is false (zero) or ambiguous (x), the false-statement is executed.
Types of port Keyword
Input port Input
Output port Output
Bidirectional port inout
1. Blocking assignment
2. Non-blocking assignment
