Latch-up in CMOS Integrated Circuits

Latch-up in CMOS Integrated Circuits

 Introduction

            In CMOS fabrication, latch-up is a malfunction which can occur as a result of improper design. Latch-up in a CMOS integrated circuit, causes unintended currents will possibly resulting with the destruction of the entire circuit, thus, it must be prevented.
 Explanation of the phenomena

            Figure 1 shows the cross section of a two-transistor CMOS integrated circuit where the nMOS is on the left hand side and the pMOS on the right hand side. As it can be seen from the figure, we can talk about a parasitic pnp transistor from source of the pMOS to the p-substrate. Furthermore a parasitic npn transistor is formed from source of the nMOS, p-substrate and the n-well. These parasitic transistors and finite resistances of n-well and p-substrate can be shown like Figure 2 [1]. Equivalent circuit of these parasitic bipolar transistors is given in Figure 3 [1].

            Figure 1 Cross section of a CMOS IC

Figure 2 Parasitic bipolar transistors in a CMOS process

            Figure 3 Equivalent circuits formed by the parasitic transistors

            As it can be clearly seen from the equivalent circuit, there is a positive feedback loop around Q1 and Q2. If a parasitic current flows through the node X and raise V_x, Q2 turns on and I_C2 increases resulting V_Y decrease. This increases I_C1 and consequently V_x increases much more. If the loop gain is equal to or greater than unity, this situation continues until an enormous current flow through the circuit in other words, until the circuit is latched up. [1]

Preventing Latch-up

            As explained above, the loop gain of the equivalent circuit shown in Figure 3 should be lesser then unity in order to prevent latch-ups. Consequently, both of process and design engineers should take steps for latch-up prevention.  Doping levels, and the other design aspects should be arranged properly in order to have low parasitic resistances and current gain of bipolar transistors. There are specific design rules to prevent latch-ups in different technologies [1].

Conclusion

            As its results may be fatal for the circuit, preventing latch-up in CMOS integrated circuit design is essential for a proper operation.
 References

            [1] Razavi, B., 2000, Design of Analog CMOS Integrated Circuits, p. 628