Why Scan Frequency should be less than Clock Frequency?

Why scan frequency should be low?

                During Testing Circuit activity increases during testing and leads to high test power dissipation. i.eDrop in power supply voltage due to IR dropDrop in voltage lowers current flowing through transistorTime taken to charge load capacitor increases.Causes

• Ground bounce
• Excessive heating =>Permanent damage in circuit
• Good chip labeled bad => unnecessary yield loss
• stuck and delay faults

Clock Speed-Up under Power Constraints

• Test clock frequency lowered to reduce power dissipation

Power dissipated in a clock cycle, ½ CV ²œ  (œ= switching power)Worst case power =½ CV ²œ _{peak    <=   power budget.}

• F _test <= (2 * power budget) / CV ²œ _peak    >=  (½)CV ²œ _peak F _test
• If œ =  œ _peak/ I    then    f= i * f test without exceeding Pbudget
• C, V constant for a circuit

Test clock can be increased when switching activity is lowStrong correlation between number of transitions in scan cells and test power dissipation.Low activity in scan chain => Scan frequency can be increased without exceeding Pbudget .