6 Simple Tips to Make a Great First Impression

I’m sure you’ve heard it before that it only takes six seconds for someone to form a first impression. So how can you use those six seconds to your best advantage? Be prepared. If you know you’re going to be meeting someone new, it pays to come to the meeting prepared.

I’ve gathered six simple suggestions that can help you feel more prepared for that next important first impression — whether you’re headed for a job interview, a new client meeting, or a party with a lot of people you don’t know well, these steps can help ease your nervousness and help you nail those six seconds.

1. Smile!
   People like other people who are friendly and open, and a nice smile can open a lot more doors than your resting grump face. Smiling also projects confidence and makes you appear trustworthy.
2. Be prepared.
   Whatever the situation, follow the Boy Scout motto and be prepared. If it’s a job interview that might mean you practice answering questions, familiarize yourself with the company, bring any required paperwork, and have a few backup copies of your resume on hand. For a presentation, practice (a lot), have all the tech you could possibly need, arrive early, know what questions are likely to be asked, and so on.
3. Do a little research.
   If you know you’re going to be meeting someone new, do a little research ahead of time. Find out their hobbies, associations they’re a part of, or causes they support. LinkedIn makes this easy, but there are also apps, like Refresh, which can deliver a dossier on your contacts before any meeting automatically. Of course, don’t act like a stalker; keep the topics to things that make sense in a business setting, like asking about a board they serve on, rather than complimenting them on their latest Facebook photos.
4. Arrive early.
   You may have heard the old saying, “To be early is to be on time; to be on time is to be late; to be late is to be sorry!” It’s especially apt when meeting someone new. Being on time shows that you’re responsible and respectful, but if you arrive a few minutes early, you’ll have time to use the restroom, check your appearance, and compose yourself before your meeting. It’s important to add extra time in case of inclement weather, traffic, finding parking, etc.
5. Turn off distractions.
   There’s nothing more embarrassing than having your phone go off in the middle of an important introduction or meeting — unless it’s actually checkingyour phone during said meeting. Set your phone to silent before you ever arrive, and, if the vibrations letting you know you’ve been retweeted are still too big a temptation, turn the whole thing off.
6. Be curious.
   When it comes to conversation skills, simply being curious will help you truly engage with the person you’re speaking to. Ask thoughtful questions and really listen to the answer, instead of using the time to plan your response.

These are just a few of my own ideas, and I’d love to hear yours. What’s your best advice for making a good first impression? Let us know in the comments below.

Thanks

Sunil Ch

Physical Design Interview Questions

1. * What is signal integrity? How it affects Timing?
2. * What is IR drop? How to avoid .how it affects timing?
3. * What is EM and it effects?
4. * What is floor plan and power plan?
5. * What are types of routing?
6. * What is a grid .why we need and different types of grids?
7. * What is core and how u will decide w/h ratio for core?
8. * What is effective utilization and chip utilization?
9. * What is latency? Give the types?
10. * What is LEF?
11. * What is DEF?
12. * What are the steps involved in designing an optimal pad ring?
13. * What are the steps that you have done in the design flow?
14. * What are the issues in floor plan?
15. * How can you estimate area of block?
16. * How much aspect ratio should be kept (or have you kept) and what is the utilization?
17. * How to calculate core ring and stripe widths?
18. * What if hot spot found in some area of block? How you tackle this?
19. * After adding stripes also if you have hot spot what to do?
20. * What is threshold voltage? How it affect timing?
21. * What is content of lib, lef, sdc?
22. * What is meant my 9 track, 12 track standard cells?
23. * What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
24. * What is setup and hold? Why there are ? What if setup and hold violates?
25. * In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum operating frequency?
26. * How R and C values are affecting time?
27. * How ohm (R), fared (C) is related to second (T)?
28. * What is transition? What if transition time is more?
29. * What is difference between normal buffer and clock buffer?
30. * What is antenna effect? How it is avoided?
31. * What is ESD?
32. * What is cross talk? How can you avoid?
33. * How double spacing will avoid cross talk?
34. * What is difference between HFN synthesis and CTS?
35. * What is hold problem? How can you avoid it?
36. * For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select? Why?
37. * What is partial floor plan?
38. * What parameters (or aspects) differentiate Chip Design & Block level design??
39. * How do you place macros in a full chip design?
40. * Differentiate between a Hierarchical Design and flat design?
41. * Which is more complicated when u have a 48 MHz and 500 MHz clock design?
42. * Name few tools which you used for physical verification?
43. * What are the input files will you give for primetime correlation?
44. * What are the algorithms used while routing? Will it optimize wire length?
45. * How will you decide the Pin location in block level design?
46. * If the routing congestion exists between two macros, then what will you do?
47. * How will you place the macros?
48. * How will you decide the die size?
49. * If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?
50. * If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?
51. * In your project what is die size, number of metal layers, technology, foundry, number of clocks?
52. * How many macros in your design?
53. * What is each macro size and no. of standard cell count?
54. * How did u handle the Clock in your design?
55. * What are the Input needs for your design?
56. * What is SDC constraint file contains?
57. * How did you do power planning?
58. * How to find total chip power?
59. * How to calculate core ring width, macro ring width and strap or trunk width?
60. * How to find number of power pad and IO power pads?
61. * What are the problems faced related to timing?
62. * How did u resolve the setup and hold problem?
63. * If in your design 10000 and more numbers of problems come, then what you will do?
64. * In which layer do you prefer for clock routing and why?
65. * If in your design has reset pin, then it’ll affect input pin or output pin or both?
66. * During power analysis, if you are facing IR drop problem, then how did u avoid?
67. * Define antenna problem and how did u resolve these problem?
68. * How delays vary with different PVT conditions? Show the graph.
69. * Explain the flow of physical design and inputs and outputs for each step in flow.
70. * What is cell delay and net delay?
71. * What are delay models and what is the difference between them?
72. * What is wire load model?
73. * What does SDC constraints has?
74. * Why higher metal layers are preferred for Vdd and Vss?
75. * What is logic optimization and give some methods of logic optimization.
76. * What is the significance of negative slack?
77. * How the width of metal and number of straps calculated for power and ground?
78. * What is negative slack ? How it affects timing?
79. * What is track assignment?
80. * What is grided and gridless routing?
81. * What is a macro and standard cell?
82. * What is congestion?
83. * Whether congestion is related to placement or routing?
84. * What are clock trees?
85. * What are clock tree types?
86. * Which layer is used for clock routing and why?
87. * What is cloning and buffering?
88. * What are placement blockages?
89. * How slow and fast transition at inputs effect timing for gates?
90. * What is antenna effect?
91. * What are DFM issues?
92. * What is .lib, LEF, DEF, .tf?
93. * What is the difference between synthesis and simulation?
94. * What is metal density, metal slotting rule?
95. * What is OPC, PSM?
96. * Why clock is not synthesized in DC?
97. * What are high-Vt and low-Vt cells?
98. * What corner cells contains?
99. * What is the difference between core filler cells and metal fillers?
100. * How to decide number of pads in chip level design?
101. * What is tie-high and tie-low cells and where it is used * What is signal integrity? How it affects Timing?
102. * What is IR drop? How to avoid .how it affects timing?
103. * What is EM and it effects?
104. * What is floor plan and power plan?
105. * What are types of routing?
106. * What is a grid .why we need and different types of grids?
107. * What is core and how u will decide w/h ratio for core?
108. * What is effective utilization and chip utilization?
109. * What is latency? Give the types?
110. * What is LEF?
111. * What is DEF?
112. * What are the steps involved in designing an optimal pad ring?
113. * What are the steps that you have done in the design flow?
114. * What are the issues in floor plan?
115. * How can you estimate area of block?
116. * How much aspect ratio should be kept (or have you kept) and what is the utilization?
117. * How to calculate core ring and stripe widths?
118. * What if hot spot found in some area of block? How you tackle this?
119. * After adding stripes also if you have hot spot what to do?
120. * What is threshold voltage? How it affect timing?
121. * What is content of lib, lef, sdc?
122. * What is meant my 9 track, 12 track standard cells?
123. * What is scan chain? What if scan chain not detached and reordered? Is it compulsory?
124. * What is setup and hold? Why there are ? What if setup and hold violates?
125. * In a circuit, for reg to reg path ...Tclktoq is 50 ps, Tcombo 50ps, Tsetup 50ps, tskew is 100ps. Then what is the maximum operating frequency?
126. * How R and C values are affecting time?
127. * How ohm (R), fared (C) is related to second (T)?
128. * What is transition? What if transition time is more?
129. * What is difference between normal buffer and clock buffer?
130. * What is antenna effect? How it is avoided?
131. * What is ESD?
132. * What is cross talk? How can you avoid?
133. * How double spacing will avoid cross talk?
134. * What is difference between HFN synthesis and CTS?
135. * What is hold problem? How can you avoid it?
136. * For an iteration we have 0.5ns of insertion delay and 0.1 skew and for other iteration 0.29ns insertion delay and 0.25 skew for the same circuit then which one you will select? Why?
137. * What is partial floor plan?
138. * What parameters (or aspects) differentiate Chip Design & Block level design??
139. * How do you place macros in a full chip design?
140. * Differentiate between a Hierarchical Design and flat design?
141. * Which is more complicated when u have a 48 MHz and 500 MHz clock design?
142. * Name few tools which you used for physical verification?
143. * What are the input files will you give for primetime correlation?
144. * What are the algorithms used while routing? Will it optimize wire length?
145. * How will you decide the Pin location in block level design?
146. * If the routing congestion exists between two macros, then what will you do?
147. * How will you place the macros?
148. * How will you decide the die size?
149. * If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?
150. * If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?
151. * In your project what is die size, number of metal layers, technology, foundry, number of clocks?
152. * How many macros in your design?
153. * What is each macro size and no. of standard cell count?
154. * How did u handle the Clock in your design?
155. * What are the Input needs for your design?
156. * What is SDC constraint file contains?
157. * How did you do power planning?
158. * How to find total chip power?
159. * How to calculate core ring width, macro ring width and strap or trunk width?
160. * How to find number of power pad and IO power pads?
161. * What are the problems faced related to timing?
162. * How did u resolve the setup and hold problem?
163. * If in your design 10000 and more numbers of problems come, then what you will do?
164. * In which layer do you prefer for clock routing and why?
165. * If in your design has reset pin, then it’ll affect input pin or output pin or both?
166. * During power analysis, if you are facing IR drop problem, then how did u avoid?
167. * Define antenna problem and how did u resolve these problem?
168. * How delays vary with different PVT conditions? Show the graph.
169. * Explain the flow of physical design and inputs and outputs for each step in flow.
170. * What is cell delay and net delay?
171. * What are delay models and what is the difference between them?
172. * What is wire load model?
173. * What does SDC constraints has?
174. * Why higher metal layers are preferred for Vdd and Vss?
175. * What is logic optimization and give some methods of logic optimization.
176. * What is the significance of negative slack?
177. * How the width of metal and number of straps calculated for power and ground?
178. * What is negative slack ? How it affects timing?
179. * What is track assignment?
180. * What is grided and gridless routing?
181. * What is a macro and standard cell?
182. * What is congestion?
183. * Whether congestion is related to placement or routing?
184. * What are clock trees?
185. * What are clock tree types?
186. * Which layer is used for clock routing and why?
187. * What is cloning and buffering?
188. * What are placement blockages?
189. * How slow and fast transition at inputs effect timing for gates?
190. * What is antenna effect?
191. * What are DFM issues?
192. * What is .lib, LEF, DEF, .tf?
193. * What is the difference between synthesis and simulation?
194. * What is metal density, metal slotting rule?
195. * What is OPC, PSM?
196. * Why clock is not synthesized in DC?
197. * What are high-Vt and low-Vt cells?
198. * What corner cells contains?
199. * What is the difference between core filler cells and metal fillers?
200. * How to decide number of pads in chip level design?
201. * What is tie-high and tie-low cells and where it is used

Short-Channel Effects in MOSFETs

Short-Channel Devices

A MOSFET device is considered to be short when the channel length is the same order of magnitude as the depletion-layer widths (xdD, xdS) of the source and drain junction. As the channel length L is reduced to increase both the operation speed and the number of components per chip, the so-called short-channel effects arise. 

Short-Channel Effects

The short-channel effects are attributed to two physical phenomena:

1. the limitation imposed on electron drift characteristics in the channel, 

2. the modification of the threshold voltage due to the shortening channel length.

In particular five different short-channel effects can be distinguished:

1. drain-induced barrier lowering and punchthrough 

2. surface scattering 

3. velocity saturation 

4. impact ionization 

5. hot electrons 

Drain-induced barrier lowering and punchthrough

The expressions for the drain and source junction widths are:

where VSB and VDB are source-to-body and drain-to-body voltages.

When the depletion regions surrounding the drain extends to the source, so that the two depletion

layer merge (i.e., when xdS + xdD = L), punchtrough occurs. Punchthrough can be minimized with

thinner oxides, larger substrate doping, shallower junctions, and obviously with longer channels.

The current flow in the channel depends on creating and sustaining an inversion layer on the

surface. If the gate bias voltage is not sufficient to invert the surface (VGS<VT0), the carriers

(electrons) in the channel face a potential barrier that blocks the flow. Increasing the gate voltage

reduces this potential barrier and, eventually, allows the flow of carriers under the influence of the

channel electric field. In small-geometry MOSFETs, the potential barrier is controlled by both the

gate-to-source voltage VGS and the drain-to-source voltage VDS. If the drain voltage is increased, the potential barrier in the channel decreases, leading to drain-induced barrier lowering (DIBL). The

reduction of the potential barrier eventually allows electron flow between the source and the drain,

even if the gate-to-source voltage is lower than the threshold voltage. The channel current that flows

under this conditions (VGS<VT0) is called the sub-threshold current.

 

Surface scattering 

As the channel length becomes smaller due to the lateral extension of the depletion layer into the channel region, the longitudinal electric field component ey increases, and the surface mobility becomes field-dependent. Since the carrier transport in a MOSFET is confined within the narrow inversion layer, and the surface scattering (that is the collisions suffered by the electrons that are accelerated toward the interface by ex) causes reduction of the mobility, the electrons move with great difficulty parallel to the interface, so that the average surface mobility, even for small values of ey, is about half as much as that of the bulk mobility.

Velocity saturation

The performance short-channel devices is also affected by velocity saturation, which reduces the transconductance in the saturation mode. At low ey, the electron drift velocity vde in the channel varies linearly with the electric field intensity. However, as ey increases above 104 V/cm, the drift velocity tends to increase more slowly, and approaches a saturation value of vde(sat)=107 cm/s around ey =105 V/cm at 300 K. 

Note that the drain current is limited by velocity saturation instead of pinchoff. This occurs in shortchannel devices when the dimensions are scaled without lowering the bias voltages. Using vde(sat), the maximum gain possible for a MOSFET can be defined as

Impact ionization

Another undesirable short-channel effect, especially in NMOS, occurs due to the high velocity of electrons in presence of high longitudinal fields that can generate electron-hole (e-h) pairs by impact ionization, that is, by impacting on silicon atoms and ionizing them. 

It happens as follow: normally, most of the electrons are attracted by the drain, while the holes enter the substrate to form part of the parasitic substrate current. Moreover, the region between the source and the drain can act like the base of an npn transistor, with the source playing the role of the emitter and the drain that of the collector. If the aforementioned holes are collected by the source, and the corresponding hole current creates a voltage drop in the substrate material of the order of .6V, the normally reversed-biased substrate-source pn junction will conduct appreciably. Then electrons can be injected from the source to the substrate, similar to the injection of electrons from the emitter to the base. They can gain enough energy as they travel toward the drain to create new eh pairs. The situation can worsen if some electrons generated due to high fields escape the drain field to travel into the substrate, thereby affecting other devices on a chip. 

Hot electrons 

Another problem, related to high electric fields, is caused by so-called hot electrons. This highenergy electrons can enter the oxide, where they can be trapped, giving rise to oxide charging that can accumulate with time and degrade the device performance by increasing VT and affect adversely the gate’s control on the drain current.