TEMPERATURE INVERSION

TEMPERATURE INVERSION

Traditionally MOSFET drive current (ID) reduced with increasing temperature. Hence for most cases worst case delay corner used to be high temperature (100C or higher, depending on target application). With transistor scaling, VDD and Vt have scaled but not as aggressively as the rest of the parameters (such as gate oxide thickness, channel length etc.). If you look at the MOSFET drive current equation,

So, ID varies linearly as u (mobility) and (V_GS-V_T)² or the overdrive voltage. Both mobility and Vt reduce with increasing temperature and viceversa. Interestingly, current is dependent on difference between Vg and Vt. So there is contention between mobility and the (Vg-Vt) term, and the one with more impact on the final current will determine if drive current increases or decreases with increasing temperature. For scaled nodes, i.e. at lower technologies VDD has scaled to values like 0.9V or lower, while Vt has not scaled as aggressively (0.3~0.4V), because of which even though mobility improves at low temperature, the increasing Vt and hence reducing (Vg-Vt) has a greater impact on the current, resulting in less drive current at lower temperature than at higher temperature. Hence, at scaled technology nodes, the low temperature becomes the SLOW corner, not HIGH temperature, especially for the HVT devices. This phenomenon is known has inverse temperature dependence in MOSFETs.

Crosstalk

Switching of the signal in one net can interference neighboring net due to cross coupling capacitance. This affect is known as cross talk. Crosstalk can lead to crosstalk-induced delay changes or static noise.

Double spacing   =>  more spacing =>less capacitance =>less cross talk
Multiple vias       =>  less resistance =>less RC delay
Shielding             =>  constant cross coupling capacitance =>known value of crosstalk
Buffer insertion   =>  boost the victim strength.
Net ordering        =>  in same metal layer change the net path.
Layer assignment =>  Change the metal layer of two nets if possible. (One s/g in metal 3 and one signal in metal 4).

Difference between DIBL AND GIDL.

GIDL:  Gate induced drain leakage is a leakage mechanism from the gate-drain overlap region caused when the Drain voltage is very high and Gate voltage is very low.The reverse biased pn junction will undergo band to band tunneling in which the electrons tunnel from the valence band of the n-type tunnel into the conduction band of the p-type and the holes tunnel vice-verse. This results in a leakage current through the gate oxide.

DIBL:  Drain induced barrier lowering is related to the reduction in the threshold voltage of the transistor due to the large depletion region created by the Drain potential.U can think of it as-since already a part of the region under the gate is depleted by the drain, only a little amount of gate potential is needed to complete depletion in the rest of the area.This means a lower threshold voltage.

What is the Difference between synchronizer and lockup latch?

What is the Difference between synchronizer and lockup latch?

A Synchronizer handles situations where data needs to move from faster clock domain to slower clock domain or vice-versa,whereas lockup latch doesn't allow data to cross between two clock domains.

Lockup latch is used to add a half cycle to avoid setup/hold issues between two flops.

Lock-up latches are used to allow scan chains to cross the clock domains. They mitigate the skew between two clock domains to ensure data is shifted reliably on the scan chain.

Latch-up in CMOS Integrated Circuits

Latch-up in CMOS Integrated Circuits

 Introduction

            In CMOS fabrication, latch-up is a malfunction which can occur as a result of improper design. Latch-up in a CMOS integrated circuit, causes unintended currents will possibly resulting with the destruction of the entire circuit, thus, it must be prevented.
 Explanation of the phenomena

            Figure 1 shows the cross section of a two-transistor CMOS integrated circuit where the nMOS is on the left hand side and the pMOS on the right hand side. As it can be seen from the figure, we can talk about a parasitic pnp transistor from source of the pMOS to the p-substrate. Furthermore a parasitic npn transistor is formed from source of the nMOS, p-substrate and the n-well. These parasitic transistors and finite resistances of n-well and p-substrate can be shown like Figure 2 [1]. Equivalent circuit of these parasitic bipolar transistors is given in Figure 3 [1].

            Figure 1 Cross section of a CMOS IC

Figure 2 Parasitic bipolar transistors in a CMOS process

            Figure 3 Equivalent circuits formed by the parasitic transistors

            As it can be clearly seen from the equivalent circuit, there is a positive feedback loop around Q1 and Q2. If a parasitic current flows through the node X and raise V_x, Q2 turns on and I_C2 increases resulting V_Y decrease. This increases I_C1 and consequently V_x increases much more. If the loop gain is equal to or greater than unity, this situation continues until an enormous current flow through the circuit in other words, until the circuit is latched up. [1]

Preventing Latch-up

            As explained above, the loop gain of the equivalent circuit shown in Figure 3 should be lesser then unity in order to prevent latch-ups. Consequently, both of process and design engineers should take steps for latch-up prevention.  Doping levels, and the other design aspects should be arranged properly in order to have low parasitic resistances and current gain of bipolar transistors. There are specific design rules to prevent latch-ups in different technologies [1].

Conclusion

            As its results may be fatal for the circuit, preventing latch-up in CMOS integrated circuit design is essential for a proper operation.
 References

            [1] Razavi, B., 2000, Design of Analog CMOS Integrated Circuits, p. 628

Why Scan Frequency should be less than Clock Frequency?

Why scan frequency should be low?

                During Testing Circuit activity increases during testing and leads to high test power dissipation. i.eDrop in power supply voltage due to IR dropDrop in voltage lowers current flowing through transistorTime taken to charge load capacitor increases.Causes

• Ground bounce
• Excessive heating =>Permanent damage in circuit
• Good chip labeled bad => unnecessary yield loss
• stuck and delay faults

Clock Speed-Up under Power Constraints

• Test clock frequency lowered to reduce power dissipation

Power dissipated in a clock cycle, ½ CV ²œ  (œ= switching power)Worst case power =½ CV ²œ _{peak    <=   power budget.}

• F _test <= (2 * power budget) / CV ²œ _peak    >=  (½)CV ²œ _peak F _test
• If œ =  œ _peak/ I    then    f= i * f test without exceeding Pbudget
• C, V constant for a circuit

Test clock can be increased when switching activity is lowStrong correlation between number of transitions in scan cells and test power dissipation.Low activity in scan chain => Scan frequency can be increased without exceeding Pbudget .

Congestion control methods

Congestion needs to be analyzed after placement and the routing results depend on how congested your design is. Routing congestion may be localized. Some of the things that you can do to make sure routing is hassle free are:

Placement blockages: The utilization constraint is not a hard rule, and if you want to specifically avoid placement in certain areas, use placement blockages.
Soft blockages (buffer only)Hard blockages (No std cells and buffers are allowed to Place)Partial blockages (same as density screens)Halo (same as soft blockage but blockage can also be moved w.r.t Macro.)

Macro-padding: Macro padding or placement halos around the macros are placement blockages around the edge of the macros. This makes sure that no standard cells are placed near the pin outs of the macros, thereby giving extra breathing space for the macro pin connections to standard cells.

Cell padding: Cell Padding refers to placement clearance applied to std cells in PnR tools. This is typically done to ease placement congestion or reserve some space for future use down the flow.
For example typically people apply cell padding to the buffers/inverters used to build clock tree, so that space is reserved to insert DECAP cells near them after CTS.

Maximum Utilization constraint (density screens): Some tools let you specify maximum core utilization numbers for specific regions. If any region has routing congestion, utilization there can be reduced, thus freeing up more area for routing.

set_congestion_options -max_util 0.6-coordinate{837 114 1103 918}